Dr. Peng Liu Profile

Dr. Peng Liu

at Zhejiang Univ

SPIE Involvement:

Author

Publications (19)

Proceedings Article | 22 February 2012 Paper

Integrated switchable ring filters on silicon for optical interconnects

Jianyi Yang, Ting Hu, Chen Qiu, Xiaoqing Jiang, Weidong Wang, Peng Liu, Mei Yang

Proceedings Volume 8333, 833304 (2012) https://doi.org/10.1117/12.919783

KEYWORDS: Silicon, Tunable filters, Optical filters, Optical interconnects, Filtering (signal processing), Microrings, Modulators, Chemical mechanical planarization, Silicon photonics, Resonators

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Proceedings Article | 11 November 2010 Paper

Digital camera auto white balance based on color temperature estimation clustering

Lei Zhang, Peng Liu, Yuling Liu, Feihong Yu

Proceedings Volume 7850, 78502J (2010) https://doi.org/10.1117/12.871051

KEYWORDS: Light sources, Digital cameras, Sensors, Sun, Image analysis, Human vision and color perception, Light, Video, Light sources and illumination, Image quality

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Proceedings Article | 10 February 2006 Paper

Media digital signal processor core design for multimedia application

Peng Liu, Guo-jun Yu, Wei-guang Cai, Qing-dong Yao

Proceedings Volume 6074, 607410 (2006) https://doi.org/10.1117/12.647520

KEYWORDS: Digital signal processing, Signal processing, Multimedia, Logic, Computer architecture, Video, Multiplexers, Magnetorheological finishing, Data processing, Video processing

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Proceedings Article | 10 February 2006 Paper

IIA: a novel method to optimize media instruction set of embedded processor

Keming Chen, Guojun Yu, Peng Liu, Qingdong Yao

Proceedings Volume 6074, 60740E (2006) https://doi.org/10.1117/12.643507

KEYWORDS: Computer architecture, Digital signal processing, Video processing, Parallel processing, Clocks, Video, Signal processing, Computer simulations, Data processing, Video coding

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Proceedings Article | 10 February 2006 Paper

System-on-chip architecture with media DSP and RISC core for media application

Peng Liu

Proceedings Volume 6074, 60740D (2006) https://doi.org/10.1117/12.643258

KEYWORDS: Video, Digital signal processing, Computer programming, Multimedia, Video processing, Signal processing, System on a chip, Control systems, Video compression, Computer architecture

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Proceedings Article | 9 December 2005 Paper

Determining thin film thickness characterization using adaptive simulated annealing algorithm

Yanping Chen, Yuling Liu, Peng Liu, Yingbo He, Feihong Yu

Proceedings Volume 6024, 602416 (2005) https://doi.org/10.1117/12.666850

KEYWORDS: Thin films, Algorithms, Evolutionary algorithms, Refractive index, Spectroscopy, Optimization (mathematics), Reflectance spectroscopy, Annealing, Reflection, Optical engineering

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Proceedings Article | 14 March 2005 Paper

A processor for MPEG decoder SOC: a software/hardware co-design approach

Guojun Yu, Qingdong Yao, Peng Liu, Zhidi Jiang, Fuping Li

Proceedings Volume 5685, (2005) https://doi.org/10.1117/12.582737

KEYWORDS: Video processing, Digital signal processing, Video, Signal processing, Video compression, System on a chip, Control systems, Algorithm development, Standards development, Radon

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Proceedings Article | 8 March 2005 Paper

32b RISC/DSP media processor: MediaDSP3201

Ce Shi, Wei-Dong Wang, Li Zhou, Lei Gao, Peng Liu, Qingdong Yao

Proceedings Volume 5683, (2005) https://doi.org/10.1117/12.586072

KEYWORDS: Digital signal processing, Control systems, Data processing, Signal processing, Data communications, Embedded systems, Multimedia, Process control, Computer architecture, Data conversion

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Proceedings Article | 8 March 2005 Paper

Pipelining and bypassing in a RISC/DSP processor

Guojun Yu, Qingdong Yao, Peng Liu, Zhidi Jiang, Fuping Li

Proceedings Volume 5683, (2005) https://doi.org/10.1117/12.583185

KEYWORDS: Digital signal processing, Multiplexers, Logic, Clocks, Computer architecture, Circuit switching, Video, Microelectromechanical systems, Network architectures, Image processing

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Proceedings Article | 28 April 2004 Paper

Speed-optimized ASIC turbo decoder core design

XiaoYi Chen, Qingdong Yao, Peng Liu

Proceedings Volume 5284, (2004) https://doi.org/10.1117/12.520206

KEYWORDS: Silicon, Digital signal processing, Field programmable gate arrays, Signal to noise ratio, Clocks, Computer programming, Wireless communications, Logic, Forward error correction, Convolution

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Proceedings Article | 19 April 2004 Paper

Novel kind of DSP design method based on IP core

Qiaoyan Yu, Peng Liu, Weidong Wang, Xiang Hong, Jicheng Chen, Jianzhong Yuan, Keming Chen

Proceedings Volume 5309, (2004) https://doi.org/10.1117/12.526060

KEYWORDS: Digital signal processing, Software development, Logic, System on a chip, Signal processing, Clocks, Microelectromechanical systems, Algorithm development, Binary data, Product engineering

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Proceedings Article | 19 April 2004 Paper

Reconfigurable hardware/software cosimulation platform for media processor

Hao Wu, Peng Liu, Weidong Wang, Zhong Cai, Qingdong Yao

Proceedings Volume 5309, (2004) https://doi.org/10.1117/12.527231

KEYWORDS: Computer simulations, Field programmable gate arrays, Signal processing, Data communications, Software development, Human-machine interfaces, Telecommunications, Digital signal processing, Multimedia, Wavelets

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Proceedings Article | 21 April 2003 Paper

Turbo decoder core design for system development

Xiaoyi Chen, Qingdong Yao, Peng Liu

Proceedings Volume 5117, (2003) https://doi.org/10.1117/12.500346

KEYWORDS: Digital signal processing, Clocks, Data compression, Field programmable gate arrays, Computer programming, Signal to noise ratio, Data storage, Telecommunications, Wireless communications, Signal processing

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Due to their near Shannon-capacity performance, turbo codes have received a considerable amount of attention since their introduction. They are particularly attractive for cellular communication systems and have been included in the specifications for both the WCDMA(UMTS) and cdma2000 third-generation cellular standards. The log-MAP decoding algorithm and some technologies used to reduce the complexity have discussed in the past days. But we can see that if we apply the Turbo code to wireless communications,the decoding process rate is the bottleneck. The software implement is not realistic in today’s DSP process rate. So the hardware design is supposed to realize the decoding. The purpose of this paper is to present a full ASIC design way of Turbo decoding. Many technologies are added to the basic Log-MAP algorithm to simple the design and improve the performance. With the log-MAP algorithm, the Jacobi logarithm is computed exactly using max*()=ln(exp(x)+exp(y))=max()+fc(|y-x|),The correction function fc(|y-x|) is important because there will be 0.5dB SNR loss without it. The linear approximation can be used and the linear parameters was selected carefully to suit hardware realize in our design. In order to save the power consumption and also to assure the performance, the quantization is important in ASIC design, we adopt a compromise scheme to save the power and also there is good BER behaves. Many noisy frames can be corrected with a few iterations while some of the more noisy frames need to experience a full number of iterations (NOI). Thus, if the decoder could stop the iteration as soon as the frame becomes correct, the average NOI would be reduced. There are many ways to stop the iteration such as CRC, compare and so on, we adopt a significantly less computation and much less storage stop criteria. For long frames the memory for storing the entire frame of the forward probability α or the backward probability β can be very large. Available products all use sliding-window version of the turbo decoder to reduce the memory requirements. This is also true in our design. In addition of this, a new method is adopted to expand the sliding window length but without increasing the storing requirement. This method also improves the performance evidently. The technologies adoped in the paper are suited hardware design for wireless application. For example, this decoding core can be embedded into our 32-bit digital signal processor (MD-32) to realize 3G basestation receiver.

Proceedings Article | 4 January 2002 Paper

Hardware/software codesign for HDTV source decoder on system level

Peng Liu, Qingdong Yao, Weijian Yang

Proceedings Volume 4671, (2002) https://doi.org/10.1117/12.453111

KEYWORDS: System on a chip, On-screen displays, Video, Video processing, Systems modeling, Computer architecture, Prototyping, Algorithm development, Control systems, Computer simulations

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Proceedings Article | 20 December 2001 Paper

Efficient RTL-based code generation for specified DSP C-compiler

Qiaohai Pan, Peng Liu, Ce Shi, Qingdong Yao, Shaobo Zhu, Li Yan, Ying Zhou, Weibing Huang

Proceedings Volume 4674, (2001) https://doi.org/10.1117/12.451069

KEYWORDS: Digital signal processing, Embedded systems, Detection and tracking algorithms, Nanoimprint lithography, Information science, Electronics engineering, Algorithm development, Standards development, Cerium, Lithium

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Proceedings Article | 20 December 2001 Paper

Hardware/software codesign for embedded RISC core

Peng Liu

Proceedings Volume 4674, (2001) https://doi.org/10.1117/12.451073

KEYWORDS: Prototyping, Computer architecture, System on a chip, Computer simulations, Software development, Interfaces, Video, Device simulation, Microelectromechanical systems, Information science

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Proceedings Article | 20 September 2001 Paper

Hardware scheme for plankton recognition

Peng Liu, Xiaoou Tang, Da Yao, Qingdong Yao

Proceedings Volume 4552, (2001) https://doi.org/10.1117/12.441520

KEYWORDS: Digital signal processing, Image processing, Detection and tracking algorithms, Image segmentation, Algorithm development, Binary data, Edge detection, Ytterbium, Neurons, Feature extraction

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Proceedings Article | 1 August 2001 Paper

SPMD architecture for DSP-based data encryption communication system

Peng Liu, Qiaohai Pan, Dongxiao Li, Qingdong Yao, Weijian Yan

Proceedings Volume 4314, (2001) https://doi.org/10.1117/12.435397

KEYWORDS: Digital signal processing, Data communications, Computer architecture, Control systems, Computing systems, Telecommunications, Data processing, Computer security, Field programmable gate arrays, Safety

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Proceedings Article | 29 March 2001 Paper

Processor architecture of MBAP for embedded image understanding system

Peng Liu, Qingdong Yao, Song Wu, Qiaohai Pan, JinMei Lai

Proceedings Volume 4313, (2001) https://doi.org/10.1117/12.420797

KEYWORDS: Image processing, Image understanding, Clocks, Array processing, Curium, Embedded systems, Switches, Multiplexers, Reconfigurable computing, Process control

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Showing 5 of 19 publications

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