Mr. Mukul Gupta Profile

Mukul Gupta

SPIE Involvement:

Author

Publications (2)

This will count as one of your downloads.

You will have access to both the presentation and article (if available).

DOWNLOAD NOW

This content is available for download via your institution's subscription. To access this item, please sign in to your personal account.

Email or Username Forgot your username?

Password Forgot your password?

Show

Keep me signed in

No SPIE account? Create an account

SPIE Journal Paper | 19 August 2013

Framework for exploring the interaction between design rules and overlay control

Rani Ghaida, Mukul Gupta, Puneet Gupta

JM3, Vol. 12, Issue 03, 033014, (August 2013) https://doi.org/10.1117/12.10.1117/1.JMM.12.3.033014

KEYWORDS: Overlay metrology, Semiconducting wafers, Photomasks, Optical alignment, Transistors, Lithography, Manufacturing, Double patterning technology, Systems modeling, Scanners

Read Abstract +

Overlay control is becoming increasingly more important with the scaling of technology. It has become even more critical and more challenging with the move toward multiple-patterning lithography, where overlay translates into CD variability. Design rules and overlay have strong interaction and can have a considerable impact on the design area, yield, and performance. We study this interaction and evaluate the overall design impact of rules, overlay characteristics, and overlay control options. For this purpose, we developed a model for yield loss from overlay that considers overlay residue after correction and the breakdown between field-to-field and within-field overlay; the model is then incorporated into a general design-rule evaluation framework to study the overlay/design interaction. The framework can be employed to optimize design rules and more accurately project overlay-control requirements of the manufacturing process. The framework is used to explore the design impact of litho-etch litho-etch double-patterning rules and poly line-end extension rule defined between poly and active layer for different overlay characteristics (i.e., within-field versus field-to-field overlay) and different overlay models at the 14-nm node. Interesting conclusions can be drawn from our results. For example, one result shows that increasing the minimum mask-overlap length by 1 nm would allow the use of a third-order wafer/sixth-order field-level overlay model instead of a sixth-order wafer/sixth-order field-level model with negligible impact on design.

Proceedings Article | 18 April 2013 Paper

A framework for exploring the interaction between design rules and overlay control

Rani Ghaida, Mukul Gupta, Puneet Gupta

Proceedings Volume 8681, 86810C (2013) https://doi.org/10.1117/12.2013619

KEYWORDS: Overlay metrology, Semiconducting wafers, Ferroelectric LCDs, Optical alignment, Photomasks, Lithography, Systems modeling, Scanners, Dysprosium, Process control

Read Abstract +

Overlay control is becoming increasingly more important with the scaling of technology. It has become even more critical and more challenging with the move toward multiple-patterning lithography, where overlay translates into CD variability. Design rules and overlay have strong interaction and can have a considerable impact on the design area, yield, and performance. This paper offers a framework to study this interaction and evaluate the overall design impact of rules, overlay characteristics, and overlay control options. The framework can also be used for designing informed, design-aware overlay metrology and control strategies. In this work, The framework was used to explore the design impact of LELE doublepatterning rules and poly-line end extension rule defined between poly and active layer for different overlay characteristics (i.e., within-field vs. field-to-field overlay) and different overlay models at the 14nm node. Interesting conclusions can be drawn from our results. For example, one result shows that increasing the minimum mask-overlap length by 1nm would allow the use of a third-order wafer/sixth-order field-level overlay model instead of a sixth-order wafer/sixth-order field-level model with negligible impact on design.

My Library

You currently do not have any folders to save your paper to! Create a new folder below.

Folder Name

Folder Description

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks. You are receiving this notice because your organization may not have SPIE eBooks access.*

*Shibboleth/Open Athens users─please sign in to access your institution's subscriptions.

To obtain this item, you may purchase the complete book in print or electronic format on SPIE.org.

ORGANIZATIONAL
Sign in with credentials provided by your organization.

Organizational Username

Organizational Password

Show/Hide Password

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

;

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members:

Non-members: ADD TO CART

Keywords/Phrases

Search In:

Publication Years