Mr. Matthew Wasilik Profile

Matthew Wasilik

Senior Development Engineer at Univ of California Berkeley

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Proceedings Article | 30 December 2003 Paper

Deep reactive ion etch conditioning recipe

Matthew Wasilik, Ning Chen

Proceedings Volume 5342, (2003) https://doi.org/10.1117/12.522941

KEYWORDS: Etching, Deep reactive ion etching, Semiconducting wafers, Plasma, Fluorine, Silicon, Ions, Photomasks, Reactive ion etching, Oxygen

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Deep Reactive Ion Etch (DRIE) has historically been regarded as a process possessing inherent variable response. These varying responses include etch rate, mask selectivity, etch depth uniformity across the wafer, and the overall profile of the features being etched. Several factors are thought to lend themselves to this observed variation. Among them are process temperature disparities and residual parasitic compounds within the reaction chamber itself. A long term experiment was carried out to examine the statistical difference between DRIE runs with and without a specially defined pre-process conditioning recipe. This recipe was developed with the expectations of serving a twofold effect: the first serving as a “warm-up” of the process chamber to a steady state temperature, and the second being a stripping of residual organic compounds within the chamber that might otherwise add variance to the following DRIE process. The pre-process recipe has duration of ~30 minutes. The results of the experiment performed will clearly show that this conditioning recipe run prior to processing reduces the typical variance of DRIE processing.

Proceedings Article | 21 November 2001 Paper

Low-frequency process for silicon-on-insulator deep reactive ion etching

Matthew Wasilik, Albert Pisano

Proceedings Volume 4592, (2001) https://doi.org/10.1117/12.449003

KEYWORDS: Etching, Silicon, Semiconducting wafers, Deep reactive ion etching, Ions, Oxides, Reactive ion etching, Power supplies, Scanning electron microscopy, Standards development

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Due to the inherently non-uniform etching effects in the standard DRIE (Deep Reactive Ion Etch) process, a new technique has been developed specifically for SOI (silicon on insulator) etching. The new system embodies a separate LF power supply that is pulsed when being applied to the platen during the etch cycle. This lends itself to assisting in the reduction of ionic charging at the insulator layer in deep trenches. Consequently, notching or footing of Si structures is disallowed. From this a decrease in over etch sensitivity emerges, with the end result being the ability to produce high-quality, large aspect ratio structures. Si etch rates in the same DRIE process may differ due to three basic effects: Aspect ratio dependent etch (ARDE), microloading (RIE-lag), and the general loading effect by which edges of the substrate etch faster than the center. When etching to a buried insulating layer these effects tend to indirectly encourage footing. The purpose of the research involved was to find optimal process parameters that would minimize footing. Factorial design of experiment technique was used to accomplish this in a two step process. First, main and second order effects on etch-rate uniformity were studied. Then, once supplied with process parameters that minimize uniformity effects, parameter settings that minimize footing were found. The end result is a purse of optimized DRIE-SOI recipes that produce superb high-aspect ratio Silicon structures.

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