Dr. Lucas Petersen Barbosa Lima Profile

Dr. Lucas Petersen Barbosa Lima

at imec

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Proceedings Article | 9 April 2024 Presentation + Paper

Patterning spacer source drain cavities in CFET devices

S. Choudhury, G. Mannaert, L. P. Lima, S. Demuynck, I. Koo, F. Lazzarino

Proceedings Volume 12958, 1295805 (2024) https://doi.org/10.1117/12.3013077

KEYWORDS: Etching, Optical lithography, Silicon, Passivation, Dielectrics, Superlattices, Nanosheets, Cadmium, Field effect transistors, Chemistry

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In conventional gate-all-around FET architecture, p-type and n-type devices are stacked on top of each other on separate devices. In Complementary FET (CFET) architecture, n-MOS and p-MOS devices are stacked in the same device on top of each other. This allows for reduction in footprint and power consumption. One of the most high aspect ratio (HAR) patterning in CFET processing comes from patterning of the gate spacer, followed by nanosheet (NSH) patterning. The HAR Spacer Source/Drain cavity area is a Si/SiGe/Dielectric superlattices bringing quite a few patterning challenges. This work discusses the challenges for the spacer opening, optimization of the profile of the source drain (SD) cavity and strategies to improve selectivity with the gate hard mask (HM). The first patterning challenge includes etching of a superlattice consisting of numerous materials, including dielectrics, while maintaining selectivity to HM. This means switching of chemistries to accommodate the patterning of these multilayers. Secondly, this patterning step needs to be highly selective to the gate HM to allow enough margin for downstream processes. The patterning step also needs to deliver vertical cavity profile. All these challenges require us to explore complex etch processes including in-situ isolation, passivation, and other etching sequences. The results and challenges for a fully patterned spacer & SD cavity as demonstrated at Imec are presented in this proceeding.

Proceedings Article | 20 March 2018 Paper

Exploration of BEOL line-space patterning options at 12 nm half-pitch and below

S. Decoster, F. Lazzarino, L. Petersen Barbosa Lima, W. Li, J. Versluijs, S. Halder, A. Mallik, G. Murdoch

Proceedings Volume 10589, 105890E (2018) https://doi.org/10.1117/12.2297183

KEYWORDS: Dielectrics, Line edge roughness, Scanning electron microscopy, Etching, Photoresist materials, Metals, Oxides

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While the semiconductor industry is almost ready for high-volume manufacturing of the 7 nm technology node, research centers are defining and troubleshooting the patterning options for the 5 nm technology node (N5) and below. The target dimension for imec’s N5 BEOL applications is 20-24 nm Metal Pitch (MP), which requires Self-Aligned multiple (Double/Quadruple/Octuple) Patterning approaches (SAxP) in combination with EUV or immersion lithography at 193 nm. There are numerous technical challenges to enable gratings at the hard mask level such as good uniformity across wafer, low line edge/width roughness (LER/LWR), large process window, and all of this at low cost. An even greater challenge is to transfer these gratings into the dielectric material at such critical dimensions, where increased line edge roughness, line wiggling and even pattern collapse can be expected for materials with small mechanical stability such as highly porous low-k dielectrics. In this work we first compare three different patterning options for 12 nm half-pitch gratings at the hard mask level: EUV-based SADP and 193i-based SAQP and SAOP. This comparison will be based on process window, line edge/width roughness and cost. Next, the transfer of 12 nm line/space gratings in the dielectric material is discussed and presented. The LER of the dielectric lines is investigated as a function of the dielectric material, the trench depth, and the stress in the sacrificial hard mask. Finally, we elaborate on the different options to enable scaling down from 24 nm MP to 16 nm MP, and demonstrate 8 nm line/space gratings with 193i-based SAOP.

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