When the VLSI technology scales down to sub 40nm process node, the application of EUV is still far from
reality, which forces 193nm ArF light source to be used at 32nm/22nm node. This large gap causes severe light
refraction and hence reliable printing becomes a huge challenge. Various resolution enhancement technologies
(RETs) have been introduced in order to solve this manufacturability problem, but facing the continuously
shrinking VLSI feature size, RETs will not be able to conquer the difficulties by themselves. Since layout
patterns also have a strong relationship with their own printability, therefore litho-friendly design methodology
with process concern becomes necessary. In the very near future, double patterning technology (DPT) will be
needed in the 32nm/22nm node, and this new process will bring major change to the circuit design phases for
sure.
In this paper, we try to solve the printability problem at the cell design level. Instead of the conventional 2-D
structure of the standard cell, we analyze the trend of the application of 1-D cell based on three emerging double
patterning technologies. Focusing on the dense line printing technology with off-axis illumination, line-end gap
distribution is studied to guide our methodology for optimal cell design.
Disconnection between design and manufacturing has become a prevalent issue in modern VLSI processes. As
manufacturability becomes a major concern, uncertainties from process variation and complicated rules have increased
the design cost exponentially. Numerous design methodologies for manufacturability have been proposed to improve
the yield. In deep submicron designs, optical proximity correction (OPC) and fill insertion have become indispensable
for chip fabrication. In this paper, we propose a novel method to use these manufacturing techniques to optimize the
design. We can effectively implement non-uniform wire sizing and achieve substantial performance and power
improvement with very low costs on both design and manufacturing sides. The proposed method can reduce up to 42%
power consumption without any delay penalty. It brings minor changes to the current design flow and no extra cost for
fabrication.
Litho-aware design methodology is the key to enable the aggressive scaling down to the future technology node.
Boundary based methodology for cellwise OPC has been proposed to account for influence from features of neighboring
cells. As technology advances toward 32 and 22 nm, more columns of features are needed as representative
environments for the boundary-based cellwise OPC. In this paper, we propose a new method that combines the fill
insertion and boundary-based cellwise OPC to reduce the mask data size as well as the prohibitive runtime of full-chip
OPC, making cell characterization more predictable. To make the number of cell OPC solutions easy to handle, we
present a new methodology which uses dummy fill insertion both inside and outside cells to solve the issue for
technologies beyond 45 nm. Experimental results show a solid 30% improvement on average and maximum edge
placement errors (EPE) over the previous work.
Model based optical proximity correction (OPC) has become necessary at 90nm technology node. Cellwise OPC is
an attractive technique to reduce the mask data size as well as the prohibitive runtime of full-chip OPC. As feature
dimensions have gotten smaller, the radius of influence for edge features has extended further into neighboring cells
such that it is no longer sufficient to perform cellwise OPC independent of neighboring cells, especially for the critical
layers. The methodology described in this work accounts for features in neighboring cells and allows a cellwise
approach to be applied to cells with a printed gate length of 45nm with the projection that it can also be applied to future
technology nodes. OPC-ready cells are generated at library creation (independent of placement) using a boundary-based
technique. Each cell has a tractable number of OPC-ready versions due to an intelligent characterization of standard cell
layout features. Results are very promising: the average edge placement error (EPE) for all metal1 features in 100
layouts is 0.731nm which is less than 1% of metal1 width; the maximum EPE for poly features reduced to 1/3, compared to cellwise OPC without considering boundaries, creating similar levels of lithographic accuracy while obviating any of the drawbacks inherent in layout specific full-chip model-based OPC.
As integrated circuits manufacturing technology is advancing into 65nm and 45nm nodes, extensive resolution
enhancement techniques (RET) are needed to correctly manufacture a chip design. The widely used RET called offaxis
illumination (OAI) introduces forbidden pitches which lead to very complex design rules. It has been observed
that imposing uniformity on layout designs can substantially improve printability under OAI. In this paper, two types of
assist features for the metal layer are proposed to improve the uniformity, printable assist feature and segmented
printable assist feature. They bring different costs on performance and manufacturing. Coupling and lithography costs
from these assist features are discussed. Optimal insertion algorithm is proposed to use both types of dummy metals,
considering trade-offs between coupling and lithography costs.
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