Patterning of sub-30 nm features using high resolution nano-imprint lithography (NIL) requires use of quartz
templates. To this end, various fabrication methods such as e-beam lithography, edge lithography, and focused ion beam
lithography were employed for the template formation. Despite significant advances using these methods, NIL
template formation process suffers from low throughput and high cost of fabrication when compared with the fabrication
of masks used in optical lithography. This is largely owing to a 4X difference in feature sizes involved for the
fabrication of NIL template and optical lithography mask. In this paper, we report on a simple, cost-effective method for
the fabrication of sub-30 nm NIL templates. Typical fabrication-time required for the formation of sub-30 nm HP
templates using conventional Gaussian beam electron beam lithography, runs into several days. Additionally, complicated
etch procedures must be employed for pattern transfer onto quartz substrates. Here we propose a low cost, simplified
fabrication process for the formation of high resolution NIL templates using wafer pattern replication. We fabricated sub-
30nmHP poly-silicon lines and spaces on silicon wafer using multiple patterning technique. These patterns were subsequently
transferred onto quartz substrates using NIL technique.
Several types of features were studied to realize a template using the triple patterning technique described above. Results of wafer printing using the said template will be discussed.
KEYWORDS: Semiconducting wafers, Photomasks, Line width roughness, Inspection, Wafer inspection, Scanning electron microscopy, Defect detection, Signal to noise ratio, Extreme ultraviolet lithography, Line edge roughness
EUVL is the strongest candidate for a sub-20nm lithography solution after immersion double-patterning. There are still
critical challenges for EUVL to address to become a mature technology like today's litho workhorse, ArF immersion.
Source power and stability, resist resolution and LWR (Line Width Roughness), mask defect control and infrastructure
are listed as top issues. Source power has shown reasonably good progress during the last two years. Resist resolution
was proven to resolve 32nm HP (Half Pitch) lines and spaces with good process windows even though there are still
concerns with LWR. However, the defectivity level of blank masks is still three orders of magnitude higher than the
requirement as of today.
In this paper, mask defect control using wafer inspection is studied as an alternative solution to mask inspection for
detection of phase defects on the mask. A previous study suggested that EUVL requires better defect inspection
sensitivity than optical lithography because EUVL will print smaller defects. Improving the defect detection capability
involves not only inspection system but also wafer preparation. A few parameters on the wafer, including LWR and
wafer stack material and thickness are investigated, with a goal of enhancing the defect capture rate for after
development inspection (ADI) and after cleaning inspection (ACI). In addition to defect sensitivity an overall defect
control methodology will be suggested, involving mask, mask inspection, wafer print and wafer inspection.
The availability of defect-free masks remains one of the key challenges for inserting extreme ultraviolet lithography
(EUVL) into high volume manufacturing, yet little data is available for understanding native defects on real masks. In
this paper, a full-field EUV mask is fabricated to investigate the printability of various defects on the mask. The
printability of defects and identification of their source from mask fabrication to handling were studied using wafer
inspection. The printable blank defect density excluding particles and patterns is 0.63/cm2. Mask inspection is shown to
have better sensitivity than wafer inspection. The sensitivity of wafer inspection must be improved using through-focus
analysis and a different wafer stack.
Extreme ultraviolet lithography (EUVL) is the most effective way to print sub-30 nm features. We characterized EUVL
readiness of the three major resist platforms for sub-30 nm half-pitch (HP) manufacturability using a full-field ASML
alpha demo tool (ADT) scanner and studied the extendibility of EUV chemically amplified resist (CAR). Based on an
"M-factor" analysis, which shows the maturity of EUV resist for 28 nm HP manufacturability, a polymer-bound
photoacid generator (PAG) resist was 78% ready, a PHS hybrid resist was 81%, and a molecular glass EUV resist was
58%. The polymer-bound resist showed good resolution for 25 nm HP using the ASML ADT. It also demonstrated fair
linewidth roughness (LWR) and a good lithographic process margin of 18% exposure latitude (EL) and 160 nm depth of
field (DOF) for 28 nm HP patterning compared with the other resist platforms, but its resist collapse and etch resistance
need to be improved for manufacturability. PHS hybrid resist showed a fair etch resistance and resist collapse
performance compared to the other resist platforms, but LWR needs to be improved. The molecular resist needs to
mature further, especially in resist collapse and iso-dense (ID) bias. When considering its many strong points and control
of lower acid diffusion, the polymer-bound PAG resist appears to be the most suitable platform for manufacturability and
EUV CAR extension. We therefore would like to encourage the development of next generation polymer-bound PAG
resist with a higher etch resistance.
A process window of 80 nm DOF was demonstrated for 26 nm HP patterning and a measurable DOF for 25 nm HP was
achieved with the polymer-bound PAG resist. Resist collapse and LWR are major issues for 22 nm HP patterning in
manufacturing. LWR improvements were achieved with various techniques, and resist collapse was greatly improved
with a novel approach that uses a residual resist layer. 16 nm HP line/space (L/S) image modulation and 18 nm HP
resolution were demonstrated with an EUV CAR, indicating that EUV CAR could be extended to sub-20 nm HP
patterning.
The two key factors in EUV lithography imaging will be flare and shadow effect among other issues. The flare which is
similar to the long range density loading effect and also known to be of high level will generate CD variation throughout
the exposure field while the EUV specific shadow effect differentiates H-V CDs along the slit. The long range character
of flare in EUV full field scanner can even affect CDs in the neighboring fields. It seems to be apparent that the major
imaging challenges for EUV lithography to be successfully adopted and applied to device manufacturing will be
determined by how smartly and effectively CD variations induced both by flare and shadow effect in the full chip level
are compensated. We investigated and assessed the previously proposed full chip level compensation strategies of the
flare and shadow effect in EUVL for the application to memory device both by simulation and experiments on the
condition of full field scanner. The effectiveness of flare compensation for the case of thin absorber mask was also
addressed together with related impact on the shadow induced H-V CD bias.
Extreme ultraviolet lithography (EUVL) is the most effective way to print sub-32 nm features. We have assessed EUVL
resist readiness for 32 nm half-pitch (HP) manufacturing, presenting process feasibility data such as resolution, depth of
focus (DOF), line edge roughness/line width roughness (LER/LWR), mask error enhancement factor (MEEF), resist
collapse, critical dimension (CD) uniformity, post-exposure delay (PED) stability, and post-exposure bake (PEB)
sensitivity. Using the alpha demo tool (ADT), a full field ASML EUV scanner, we demonstrate the feasibility of a k1
~0.593 resist process for 32 nm HP line/space (L/S) patterning. Exposure latitude (EL) was 13% at best focus, and DOF
was 160 nm at best dose using a 60 nm thick resist. By incorporating a spin-on underlayer, the process margin could be
improved to 18.5% EL and 200 nm DOF. We also demonstrate ADT extendibility using a state-of-the-art EUV
platform. A k1 ~0.556 resist process was demonstrated for 30 nm HP L/S patterns, providing a 13% EL, 160 nm DOF,
and a common process window with isolated lines. 28 nm HP patterning for a k1 ~0.528 resist process could be feasible
using a more advanced resist with improved DOF and resist collapse margin.
Extreme ultraviolet lithography (EUVL) is one of the leading candidates for next-generation lithography technology for
the 32 nm half-pitch node and beyond. We have evaluated the Alpha Demo Tool(ADT) characterizing for mixed-andmatched
overlay(MMO), flare noise, and resolution limit. For process integration, one of the important things in EUVL
is overlay capability. We performed an overlay matching test of a 1.35NA and 193 immersion tool using a low thermal
expansion material(LTEM) mask. We also investigated the flare level of the EUV ADT for device applications. The
current EUV tool has a higher flare level than ArF lithography tools. We applied a contact layer for 40nm node device
integration to reduce the variation in critical dimension(CD) from the flare noise.
Flare in EUV mirror optics has been reported to be very high and long range effect due to its character which is inversely
proportional to the 4th order of wavelength. The high level of flare will generate CD (Critical Dimension) variation
problem in the area where the gradient of aerial pattern density is large while the long range influencing character would
confront an issue of computational challenge either for OPC (Optical Proximity Correction) modeling or for any other
practical ways to accommodate such a long range effect. There also exists another substantial challenge of measuring
and characterizing such a long range flare accurately enough so that the characterized flare can successfully be used for
the compensation in the standard OPC flow.
As VLSI products are being developed rapidly, design rules of semiconductor devices are correspondingly shrinking. Therefore, the electric couplings between adjacent lines are increasing and this phenomenon requires control of critical dimension uniformity (CDU) more tightly. In addition to that, the development of lithography tool for sub- 40nm design rule (D/R) is being delayed, which makes most IC manufacturer drive double patterning technology (DPT) as next generation lithography (NGL) solution. CD control is one of critical issues to implement DPT for mass production, because CD of 1st pattern affects the formation of 2nd pattern seriously so that the uniformity of 1st pattern is more important.
In this paper, the improvement of CD uniformity is investigated, especially for 3Xnm flash device for where double patterning technique is applied. Several methods have been considered or evaluated to improve CD uniformity. Among them, DoseMapperTM of ASML shows promising results. Using this system, in field uniformity (IFU) & in wafer uniformity (IWU) are improved 14% in 3&sgr;. To be implemented as a technology for mass production and to maintain the best performance, several efforts in terms of metrology and process will be further discussed in this paper.
Extreme ultraviolet lithography (EUVL) is one of the leading candidates for next-generation lithography technology for
the 32 nm half-pitch node and beyond. The availability of EUV resists is one of the most significant challenges facing its
commercialization. A successful commercial EUV resist must simultaneously meet resolution, line width roughness
(LWR), photosensitivity, and resist outgassing specifications. Photosensitivity is of particular concern because it couples
directly to source power requirements and the source is widely viewed as the most daunting challenge facing EUV
commercialization.
To accelerate EUV resist development, SEMATECH has two programs that provide the resist community access to EUV
exposure capability: 1) the EUV Resist Test Center (RTC) at SEMATECH at Albany, SUNY, and 2) the SEMATECH
microexposure tool (MET) at Lawrence Berkeley National Laboratory. SEMATECH uses both facilities to benchmark
EUV resists in close cooperation with resist suppliers.
Here we summarize results from the SEMATECH EUV resist benchmarking project including process windows,
exposure latitude, and depth of focus, photospeed, LWR, and ultimate resolution. Results show that EUV resists meet
resolution and outgassing requirements for the 32nm half-pitch node. LWR and photospeed, however, remain a concern
especially for contact-hole printing. Moreover, progress towards the 22nm half-pitch node has also been demonstrated in
terms of resolvability.
Microfield exposure tools (METs) continue to play a dominant role in the development of extreme ultraviolet (EUV)
resists. Here we present an update on the SEMATECH Berkeley 0.3-NA MET and summarize the latest test results from
high-resolution line-space and contact-hole printing. In practice, the resolution limit of contact-hole printing is generally
dominated by contact size variation that is often speculated to originate form shot noise effects. Such observations of
photon-noise limited performance are concerning because they suggest that future increased resist sensitivity would not
be feasible. Recent printing data, however, indicates that the contact size variation problem is currently not a result of
shot noise but rather attributable to the mask in combination with the resist-dominated mask error enhancement factor
(MEEF). Also discussed is the importance of the contribution of the system-level line-edge roughness (LER) to resist
LER values currently obtained with the SEMATECH Berkeley MET. We present the expected magnitude of such effects
and compare the results to observed trends in LER performance from EUV resists over the past few years.
As k1 factor approaches the theoretical limit, optical proximity correction (OPC) treatments necessary to maintain dimensional tolerances involve increasingly complex correction shapes. This translates to more detailed, or larger mask pattern databases. Moreover, development of exposure tools lags behind the shrinkage of device. This may result in dwindling of process margin in lighographic process despite using all possible resolution enhancement techniques (RETs). Although model-based OPC may lose its effectiveness in case of narrower photolithographic process margin, model-based OPC is recognized as a robust tool to cope with the diversity of layout. By the way, in case of narrower photolithographic process margin, model-based OPC lose its effectiveness. To enhance the usefulness of the OPC, we need to overcome many obstacles. It is supposed that the original layout be designed friendly to lithography to enhance the process margin using aggressive RETs, and is amended by model-based OPC to suppress the proximity effect. But, some constraints are found during an OPC procedure. Ultimately, unless the original lithgraphy friendly layout (LFL) is corrected in terms of pitches and shapes, the lithography process is out of process window as well as makes pattern fidelity poor. This paper emphasizes that the application of model-based OPC requires a particular and unique layout configuration to preserve the process margin in the low k1 process.
The on-chip variation (OCV) should be critically controlled to obtain the high speed performance in logic devices. The variation from proximity dominantly contributes to OCV. This proximity effect can be compensated by applying well-treated optical proximity correction (OPC). Therefore, the accuracy of OPC is needed, and methods to enhance its result have to be devised. The optical proximity behaviors are severely varied according to the material and optical conditions. In point of material, the proximity property is affected by species of photo-resist (PR) and change of post exposure bake (PEB) conditions. 3σ values of proximity variation are changed from 9.3 nm to 15.2 nm according to PR species. Also, proximity variations change from 16.2 nm to 13.8 nm is observed according to PEB condition. Proximity variations changes of 11.6 nm and 15.2 nm are measured by changing the illumination condition. In order not to seriously deteriorate OPC, these factors should be fixed after the OPC rules are extracted. Proximity variations of 11.4 nm, 13.9 nm and 15.2 nm are observed for the mask mean-to-targets (MTT) of 0 nm, 2nm, and 4nm, respectively. The decrease the OPC grid size enhances the correction resolution and the OCV is reduced. The selective bias rule is generated by model using grid size of 1 nm and 0.5 nm. For the nominal CD of 87 nm, proximity variations are measured to be 14.6 nm and 11.4 nm for 1 nm and 0.5 nm grid sizes, respectively. The enhancement amount of proximity variations are 9.2 nm corresponding to 39% improvement. The CD uniformity improvement for adopting the small grid size is confirmed by measuring the CD uniformity on real SRAM pattern. CD uniformities are measured 11nm and 9.1nm for grid size of 1 nm and 0.5 nm, respectively. 22% improvement of the CD uniformity is achieved.
The feasibility of sub-100 nm patterning with ArF lithography has been studied. We used ArF 0.63 NA exposure tool and investigated process windows. In-house resist (DHA-H110) and bottom anti-reflective coating material (HEART004) are used as well as commercial ones. To print sub-100 nm patterns we used the resolution enhancement technology (RET) that is extreme off-axis illumination (OAI) such as dipole and strong annular. To predict the result and compare with experimental data our simulation tool HOST (Hyundai OPC Simulation Tool) based on diffused aerial image model (DAIM) was used. Although the infrastructure of ArF lithography is not mature enough, we got a good result. For 95 nm and 90 nm patterns we could get more than 8% exposure latitude (EL) and 0.3 micrometer depth of focus (DOF). For isolated gate pattern sub-70 nm pattern was printed and we have got the characteristics of 70 nm periphery transistor. For contact hole (C/H) patterns it was more effective to use KrF lithography because resist thermal flow process (RFP) can be used to shrink C/H size. With RFP we printed up to 50 nm C/H patterns. Through this study we found that k1 value can be reduced up to 0.29 and ArF lithography can be applied for 70 nm node with high contrast resist and high NA exposure tool.
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