Semiconductor manufacturing’s full chip RET/OPC operations rely on the process models calibrated against metrology data collected from custom designed test structures. Physics-based compact models and machine learning models inherently carry the issue of model coverage often synonymous with calibration test pattern coverage. Therefore, process models frequently fail to predict unseen patterns within error tolerance. With the push for advanced technology node, such events can even occur after a node is declared HVM ready. Foundries have been combating the model coverage deficiency through costly model revisions, or expensive repair flows. There has always been the desire to have capability to screen and enhance compact model of potential coverage issue. In this paper, we use the machine learning clustering platform to learn the signatures of the model calibration test patterns and then compare them to the new design patterns in terms of feature vectors’ space correlated to model parameters’ space. The comparison provides not only the locations of the new patterns but also the similarity ranking with respect to the reference pattern, so that those patterns can be included and be further analyzed for better model coverage. These patterns are often suitable candidates to be included into new model calibration set. In this application, full chip capability is also essential besides the accuracy of the learning. The full-chip pattern check needs to be done quickly and efficiently; hence this technology could be adopted for new chip screening, highlighting areas worth paying extra attention to during inspection.
In this paper, we will evaluate model assisted rule base SRAF. Model assisted rule base SRAF
combines the advantage of both model based SRAF and rule base SRAF to ensure high process margin
without the mask making difficulty with stable wafer output. Model will assist in generating a common rule
for rule based SRAF. Method to extract the rule from the models will first be discussed. Model assisted rule
based SRAF will be applied to 3Xnm DRAM contact. Evaluation and analysis of the simulated and actual
wafer result will be discussed. Our wafer result showed that by applying Model assisted rule based SRAF
showed nearly equal performance to models based SRAF with clearly better stability and mask fabrication
feasibility.
As the optical lithography advances into the sub-30nm technology node, the various candidates of lithography have
been discussed. Double dipole lithography (DDL) has been a primary lithography candidate due to the advantages of a
simpler process and a lower mask cost compared to the double patterning lithography (DPL). However, new DDL
requirements have been also emerged to improve the process margin and to reduce the mask-enhanced error factor
(MEEF), which is to maximize the resolution and image contrast. There are two approaches in DDL i.e. model basedand
rule based-DDLs. Rule-based DDL, in which the patterns are decomposed by the simple rules such as x- and ydirectional
rules, shows the low process margin in the 2-dimension (2D) patterns, i.e., line-end to line-end, line-end to
bar and semi-isolated bars.
In this paper, we first present various analyses of our new model-based DDL (MBDDL) method. Our goal is to
maximize the process margin of the 2D patterns. Our main contributions are as follows. (1) We generate new 2D test
patterns including various configurations of the metal layer. The new 2D patterns can be used to optimize the parameters
of the MBDDL and to build the good design rules. The purpose of building the good design rules is improving the
process margin of the certain 2D patterns with the low process margin in spite of optimizing the parameters of MBDDL.
(2) We optimize the initial layout decomposition, which is the first step of MBDDL and affects the whole of MBDDL
quality. In addition, the model-based decomposition is applied with the process-window OPC (PWOPC) in terms of the
criteria of edge placement error (EPE) and mask rule checking (MRC) violation. Our new model-based approach
including the newly designed test patterns and optimized decomposition parameters leads to the improved depth of focus
(DOF) and enhanced the exposure latitude (EL). We achieve the 80nm DOF, which is the manufacturable margin for the
metal 1 layer at the sub-30nm node.
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