Immersion based 20nm technology node and below becoming very challenging to chip designers, process and integration due to multiple patterning to integrate one design layer . Negative tone development (NTD) processes have been well accepted by industry experts for enabling technologies 20 nm and below. 193i double patterning is the technology solution for pitch down to 80 nm. This imposes tight control in critical dimension(CD) variation in double patterning where design patterns are decomposed in two different masks such as in litho-etch-litho etch (LELE). CD bimodality has been widely studied in LELE double patterning. A portion of CD tolerance budget is significantly consumed by variations in CD in double patterning.
The objective of this work is to study the process variation challenges and resolution in the Negative Tone Develop Process for 20 nm and Below Technology Node. This paper describes the effect of dose slope on CD variation in negative tone develop LELE process. This effect becomes even more challenging with standalone NTD developer process due to q-time driven CD variation. We studied impact of different stacks with combination of binary and attenuated phase shift mask and estimated dose slope contribution individually from stack and mask type. Mask 3D simulation was carried out to understand theoretical aspect. In order to meet the minimum insulator requirement for the worst case on wafer the overlay and critical dimension uniformity (CDU) budget margins have slimmed. Besides the litho process and tool control using enhanced metrology feedback, the variation control has other dependencies too. Color balancing between the two masks in LELE is helpful in countering effects such as iso-dense bias, and pattern shifting. Dummy insertion and the improved decomposition techniques [2] using multiple lower priority constraints can help to a great extent. Innovative color aware routing techniques [3] can also help with achieving more uniform density and color balanced layouts.
Requalifying semiconductor photomasks remains critically important and is increasingly challenging
for 20nm and 14nm node logic reticles. Patterns are becoming more complex on the photomask,
and defect sensitivity requirements are more stringent than ever before. Reticle inspection tools
are equally important for effective process development and the successful ramp and sustained
yield for high volume manufacturing. The inspection stages considered were: incoming inspection
to match with Mask Shop Outgoing result and to detect defects generated during transport;
requalification by routine cycle inspection to detect Haze and any other defects; and inspection by
in-house or Mask shop at the post cleaning. There are many critical capability and capacity factors
for the decision for best inspection tool and strategy for high volume manufacturing, especially
objective Lens NA, wavelength, power, pixel size, throughput, full-automation inspection linked
with Overhead Transport, algorithm application, engineering application function, and inspection
of PSM and OMOG . These tools are expensive but deliver differentiated value in terms of
performance and throughput as well as extendibility. Performing a thorough evaluation and
making a technically sound choice which explores these many factors is critical for success of a
fab. This paper examines the methodology for evaluating two different photomask inspection
tools. The focus is on ensuring production worthiness on real and advanced product photomasks
requiring accurate evaluation of sensitivity, throughput, data analysis function and engineering
work function on those product photomasks. Photomasks used for data collection are production
reticles, PDM(Program defect Mask), SiN spray defect Reticle which is described that evaluates
how the tools would perform on a contaminated plate.
EUV technology has steadily progressed over the years including the introduction of a pre-production NXE:3100 scanner that has enabled EUV process development to advance one step closer to production. We have carried out the integration with 20/14nm metal layer design rules converting double patterning with ArF immersion process to EUV with a single patterning solution utilizing a NXE3100 exposure tool. The exercise through the integration of a mature test chip with an EUV level has allowed us to have early assessment of the process challenges and new workflow required to enable EUV to the mass production stage. Utilizing the NXE3100 in IMEC, we have developed an OPC model and a lithography process to support 20/14nm node EUV wafer integration of a metal layer in conjunction with immersion ArF. This allows early assessment of mix-and-match overlay for EUV to immersion system that is critical for EUV insertion strategy as well as further understanding of the litho process, OPC, and mask defect control specific to EUV single patterning. Through this work we have demonstrated high wafer yields on a 20nm test vehicle utilizing single EUV Metal layer along with additional ArF immersion levels. We were able to successfully demonstrate low mask defectivity and good via chain and open/short electrical yield. This paper summarize the learning cycles from mask defect mitigation and mix machine overlay through post metal CMP wafer integration highlighting the key accomplishments and future challenges.
As the process nodes continue to shrink, overlay budgets are approaching theoretical performance of the tools. It becomes even more imperative to improve overlay performance in order to maintain the roadmap for advance integrated circuit manufacturing. One of the critical factors in 20nm manufacturing is the overlay performance between the Middle of Line (MOL) and the Poly layer. The margin between these two layers was a process limiter, it was essential that we maintain a very tight overlay control between these layers. Due to various process and metrology related effects, maintaining good overlay control became a challenge. In this paper we describe the various factors affecting overlay performance and the measures taken to mitigate or eliminate said factors to improve overlay performance.
Flare (stray light) is an important effect impacting extreme ultraviolet lithography (EUVL) imaging system performance. Four flare measurement methods including Kirk, modulation transfer function, double exposure, and zonal ring approximation method are reviewed and analyzed theoretically. The point spread function of an EUV NXE:3100 exposure tool is extracted from the measured Kirk flare (KF) and fitted with a double-fractal model. The KF for this NXE:3100 tool is determined to be 8.5% for a 2-μm diameter absorber pad placed in a 12-mm outer radius bright field, which is larger than the previous 5% KF data measured by ASML and IMEC in 2011. The observation of the increased flare level in the NXE:3100 tool suggests that contamination of EUV optics may be a potential problem for EUVL manufacturing.
Assuming that all exposure tools on which a certain production reticle is being used are from same type and configuration it can be expected that the performance of the reticle should be independent from the exposing machines. When planning or performing arrangements for process transfer between different production sites or capacity expansion within one site performing a proximity matching between different exposure tools is a common activity. One of the objectives of a robust optical proximity correction (OPC) model is to simulate the process variation. Normally, the wafer critical dimension (CD) calibration of an OPC model is applied for one specific scanner first. In order to enhance the tolerance of the OPC model so called fingerprints of different scanners should be matched as closely as possible. Some examples of features for fingerprint test patterns are “critical dimension through pitch” (CDTP), “inverse CDTP”, “tipto-tip” and “linearity patterns”, and CD difference of disposition structures. All of them should also be matched as tightly as possible in order to reduce the process variation and to strengthen the tolerance of an OPC model. However, the focus difference between nested and isolated features which is directly influenced by different exposure tools and reticle layers will have an effect on the proximity matching of some patterns such as inverse CDTP and uniformly distributed disposition structures. In this manuscript the effects of focus differences between nested and isolated features for scanner proximity matching will be demonstrated. Moreover, the results for several scanners and different mask layers using advanced binary mask blank material will also be investigated. Even if some parts of the proximity features are closely enough to each other different parity proximity patterns will be affected by the focus difference between dense and isolated features. Because the focus difference between isolated and dense features is dependent on the illumination conditions, different mask layers applied for a proximity correction will lead to different results. The effects of source variations causing isolated and dense feature focus differences between scanners for 28 nm poly, 1X metal and contact layers will be illustrated.
The transition into smaller nodes has resulted in stringent CD tolerance requirements and the role of mask LER in that budget is not sufficiently understood. The critical variables associated with mask LER were explored with the goal of establishing mask requirements based on wafer requirements. A systematic study of the impact of mask LER correlation length (ξ), critical exponent (α) and standard deviation of the line edge (σ) on the printability of 7nm node line/space (L/S) and contact holes (CH) in extreme ultraviolet lithography has been simulated. An experimentally relevant range of the three mask LER variables was explored in these simulations. CDU and CER/LER were the primary metrics used to gauge printability and they were evaluated as a function of ξ, α and σ with stochastic simulations. A 45nm pitch was investigated to determine critical mask LER parameters that mark printability transition regions relevant to the 7nm node middle of line.
The objective of this work was to study the trench and contact hole shrink mechanism in negative tone develop resist processes and its manufacturability challenges associated for 20nm technology nodes and beyond. Process delay from post-exposure to develop, or “queue time”, is studied in detail. The impact of time link delay on resolved critical dimension (CD) is fully characterized for patterned resist and etched geometries as a function of various process changes. In this study, we assembled a detailed, theoretical model and performed experimental work to correlated time link delay to acid diffusion within the resist polymer matrix. Acid diffusion is determined using both a modulation transfer function for diffusion and simple approximation based on Fick’s law of diffusion.
Although the k1 factor is large for extreme ultraviolet (EUV) lithography compared to deep ultraviolet (DUV)
lithography, OPC is still needed to print the intended patterns on the wafer. This is primarily because of new
non-idealities, related to the inability of materials to absorb, reflect, or refract light well at 13.5nm, which must
be corrected by OPC. So, for EUV, OPC is much more than conventional optical proximity correction. This work
will focus on EUV OPC error sources in the context of an EUV OPC specific error budget for future technology
nodes. The three error sources considered in this paper are flare, horizontal and vertical print differences, and
mask writing errors. The OPC flow and computation requirements of EUV OPC are analyzed as well and
compared to DUV. Conventional optical proximity correction is simpler and faster for EUV compared to DUV
because of the larger k1 factor. But, flare and H-V biasing make exploitation of design hierarchy more difficult.
Wafer topography structures in the implant lithography process, which include the shallow trench isolation and the poly
gate, can result into a severe degradation of the resist profile and significant critical dimension variation. While bottom
anti-reflective coating (BARC) is not suitable for the implant lithography because of the plasma induced substrate
damage, developable bottom anti-reflective coating (DBARC) is now the most promising solution to eliminate wafer
topography effects for the implant layer lithography. Currently, some challenges still remain to be solved and DBARC is
not ready for mass production yet. In this study, a novel method is proposed to improve wafer topography effects by use
of sub-resolution features. Compared with DBARC, this new approach is much more cost effective. Numerical study by
use of Sentaurus-Litho simulation tool shows that the new method is promising and deserves more comprehensive
investigation.
As the advanced IC device process shrinks to below sub-micron dimensions (65nm, 45 nm
and beyond), the overall CD error budget becomes more and more challenging. The impact of
lithography process parameters other than exposure energy and defocus on final CD results cannot be
ignored any more.
In this paper we continue the development of the advanced lithography parameters model
which we presented last year. This year we achieved to decouple 4 lithography parameters: exposure,
focus, PEB temperature and laser bandwidth (or z-blur). To improve the accuracy and precision of the
model, new scatterometry marks are designed to reduce the pitch dependent accuracy impact of
sidewall angle and photoresist height for scatterometry metrology. The concept of this kind of
scatterometry mark design is from T.A. Brunner's paper "Process Monitor Gating" [SPIE Vol. 6518,
2007]. With this concept, new scatterometry marks are designed to increase the accuracy of
scatterometry measurement without sacrificing the process sensitivity and thus improve the model
prediction accuracy.
As the advanced IC device process shrinks to below sub-micron dimensions (65nm, 45 nm and beyond), the
overall CD error budget becomes more and more challenging. The impact of lithography process parameters other than
exposure energy and defocus on final CD results cannot be ignored any more.
In this paper we continue the development of an advanced control system, which can be used to detect, classify
and correct up to 5 lithography parameters. Sets of focus exposure matrix (FEM) models are first set up with different
DOE process conditions split. And photoresist profiles of specially designed scatterometry CD mark are then fitted to
models (Neural Network Model or standard polynomial model). Based on these calibrated models, not only exposure and
defocus but also PEB temperature, lens aberration, etc. can be estimated. This approach utilizes information of resist CD,
height, sidewall and feature type dependent bias to classify different lithography parameters and therefore can give very
accurate estimation of lithography parameters like energy, focus, PEB, spherical aberration and coma aberration. The
new approach does not need phase shift mask or other specially designed mask, so it can be used by most of mass
production Fabs and used for process monitoring and matching on inline production wafer.
KEYWORDS: Critical dimension metrology, Data modeling, Statistical analysis, Lithography, Photoresist materials, Statistical modeling, Process modeling, Electroluminescence, Finite element methods, Monte Carlo methods
In this paper we present one application of our new Advanced Lithography Parameters Extraction (ALPE)
system in the lithography process window analysis.
Compared with traditional DOF/EL based process window analysis or Monte Carlo approaches with pre-assumed
process variations, our new approach uses real-life process variations (exposure, focus, and even PEB
temperature, etc. if needed) collected by the new ALPE system. Different from pre-assumed process variations and
independently measured process variations, all these process variations are directly correlated with inline CD variations,
so we call them real-life process variations. Based on these real-life process variations, the estimation of final CD
uniformity will be more accurate and objective. Comparing estimated CD uniformity of new process with CD uniformity
of baseline process, it is possible for us to tell which process is better from statistical point of view.
In this paper, we study the feasibility of using a new system to set up offline critical dimension scanning electron
microscope (CDSEM) recipes for both litho and etch processes monitoring in a foundry environment before first silicon.
We will automatically create CDSEM measurement recipes based on CAD design data (2) and litho illumination
information. The main advantages of having recipes setup done through this method as compared to performing recipe
creation on the CDSEM tool itself are the reduction in CD-SEM tool usage and more importantly, the availability of the
recipes before the first wafer is being processed in lithography resulting in a faster of cycle time for new devices.
To facilitate our objective, a new feature was implemented in the design to provide a universal global alignment (GA)
feature under both optical and SEM view. The global alignment serves two functions: to minimize device-to-device and
layer-to-layer optical variation. It synchronizes design (CAD) and wafer coordinate systems. With this universal
alignment feature available across all production layers of interest, we can fully automate recipe creation process from
design to production.
KEYWORDS: Semiconducting wafers, Optical alignment, Metals, Scanning probe microscopy, Overlay metrology, Scanners, Back end of line, Chemical mechanical planarization, Signal detection, Sensors
As the critical dimension (CD) in integrated circuit (IC) device reduces, the total overlay budget needs to be more stringent. Typically, the allowable overlay error is 1/3 of the CD in the IC device. In this case, robustness of alignment mark is critical, as accurate signal is required by the scanner’s alignment system to precisely align a layer of pattern to the previous layer. Alignment issue is more severe in back-end process partly due to the influenced of Chemical Mechanical Polishing (CMP), which contribute to the asymmetric or total destroy of the alignment marks. In this paper, the performance of different design of alignment marks on 0.10μm echnology wafer has been evaluated using ASML ATHENATM alignment system. For example, segmented marks with smaller dimensions in terms of width and length are used. Narrow marks are preferable due to the space constraint in the scribe lines. The width of NSPM has been shrunk down to 70% of the SPM and the length remains the same. It is a challenge to the alignment system to collect the NSPM signal and provide comparable alignment capability. The evaluations were completed using short loop wafers, which focus on back-end-of-line via and metal layers in a 90nm Cu dual damascene low k process. The results also look into the overlay performance using different alignment strategies. Offline overlay measurements were performed to verify the results.
Line-edge roughness (LER) has been identified to cause variation in critical dimension that affects the fidelity of pattern transfer and results in greater variation in device electrical performance. In present study, the effects of aerial image quality and resist processing parameters on the severity of LER are studied. Two chemically amplified resists (CARs) with both acetal and ESCAP-type protection groups are tested and compared. It is found that the image-log-slope (ILS) at pattern edge and the resist contrast are the two major factors affecting the magnitude of LER. The ILS is alterable by pattern density, pattern width, defocus conditions and the application of PSM. On the other hand, the shape and slope of the contrast curve are dependent on both soft bake and post-exposure bake temperature. Due to the finite contrast of resist, solubility change occurs across some dose interval. This corresponds to a boundary width at the aerial image that dictates the transition zone across the pattern edge. As the boundary width region is associated with higher roughness film, smaller boundary width could be translated to better LER. Nevertheless, a three-step development model is used to explain the dependence of LER on pattern density. Basically the discrepancy is due to differential progress of the development front at different ILS when developing time is fixed. In addition, changing the shape and slope of the resist contrast curve through different processing routes could directly modify the boundary width and therefore the LER. The attributes causing different LER performances of the two resists are also discussed.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.