Optical data center networks are becoming an increasingly promising solution to solve the bottlenecks faced by electrical networks, such as low transmission bandwidth, high wiring complexity, and unaffordable power consumption. However, the optical circuit switching (OCS) network is not flexible enough to carry the traffic burst while the optical packet switching (OPS) network cannot solve the packet contention in an efficient way. To this end, an improved switching strategy named OPS with multi-hop Negative Acknowledgement (MPNACK) is proposed. This scheme uses a feedback mechanism, rather than the buffering structure, to handle the optical packet contention. The collided packet is treated as a NACK packet and sent back to the source server. When the sender receives this NACK packet, it knows a collision happens in the transmission path and a retransmission procedure is triggered. Overall, the OPS-NACK scheme enables a reliable transmission in the buffer-less optical network. Furthermore, with this scheme, the expensive and energy-hungry elements, optical or electrical buffers, can be removed from the optical interconnects, thus a more scalable and cost-efficient network can be constructed for cloud computing data centers.
KEYWORDS: Microresonators, Network on a chip, Optical networks, Waveguides, Optical design, Switching, Signal processing, Signal attenuation, Data processing, Optical engineering
The optical network on-chip is a popular option due to its low latency and high bandwidth with significantly lower power dissipation. A butterfly-fat-tree based optical network on-chip (BONoC) is designed with new optical router architecture. A hybrid signaling scheme is designed with the control information transferred and processed in the electronic domain. An energy efficient routing is proposed by considering the power consumption of the microresonators and signaling progress. Evaluation of the new optical butterfly-fat-tree NoC is made in three aspects-energy, latency, and throughput. The comparison of power consumption with its electronic counterpart shows that 64-core ONoC can save about 78.6% energy when compared to an electronic one of the same size. Finally, we simulate butterfly-fat-tree ONoC, and show the end-to-end delay and throughput with different traffic loads and various packet sizes.
KEYWORDS: Network on a chip, Network architectures, Switches, Photonics, Optical networks, Control systems, Fourier transforms, System on a chip, Switching, Electro optics
A large number of IP cores will be included in the future systems-on-chip (SoC). Traditional bus-based architectures are
no longer suitable for modern chip design, since it is difficult to expand, consumes much power and takes much area.
Network-on-chip (NoC), which employs networks to replace buses as a scalable global communication platform, has
been proposed to cope with these problems. However, limited bandwidth, long delay and high power consumption will
become bottlenecks as NoC scales to large sizes. Based on silicon optical interconnect, optical network-on-chip (ONoC)
can offer significant bandwidth and power advantages, which provides a promising solution to overcome these
limitations. In this paper, we simulated and compared several ONoCs based on the topologies including 2D Mesh, 3D
Mesh, 2D Fat Tree(FT) and 2D Butterfly Fat Tree(BFT) in terms of the end-to-end delay and network throughput. The
results showed that 3D Mesh has the best performance among the listed topologies.
Nanoscale CMOS technologies are posing new network on chip concepts to IC designers. However, the electronic
network on chip design faces many problems like energy consumption, long delay and limited bandwidth. Hence, optical
network on chip appears as a good candidate to solve these problems. The advances in nanophotonic technology make it
more realistic. A new sparse mesh is proposed for optical network on chip. Two types of non-blocking optical node
architecture are also proposed to build up core node and switch node. The new architecture fully utilizes the property of
XY routing in 2D mesh network, thus saving the number of microring resonators used. The comparisons are made with
traditional mesh in number of microring resonators, loss and energy. The results show that the proposed sparse mesh
achieves the best in all the aspects. For example, it uses 68% less number of resonators than the traditional mesh. We
simulated 2D sparse mesh optical network on chip, and showed network performance under different traffic loads and
data sizes. The results show sparse mesh achieves lower average delay and higher throughput than the traditional mesh.
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