Future infrared remote sensing systems, such as monitoring of the Earth’s environment by satellites, infrastructure inspection by unmanned airborne vehicles etc., will require 16 bit depth infrared images to be compressed and stored or transmitted for further analysis. Such systems are equipped with low power embedded platforms where image or video data is compressed by a hardware block called the video processing unit (VPU). However, in many cases using two 8-bit VPUs can provide advantages compared with using higher bit depth image compression directly. We propose to compress 16 bit depth images via 8 bit depth codecs in the following way. First, an input 16 bit depth image is mapped into 8 bit depth images, e.g., the first image contains only the most significant bytes (MSB image) and the second one contains only the least significant bytes (LSB image). Then each image is compressed by an image or video codec with 8 bits per pixel input format. We analyze how the compression parameters for both MSB and LSB images should be chosen to provide the maximum objective quality for a given compression ratio. Finally, we apply the proposed infrared image compression method utilizing JPEG and H.264/AVC codecs, which are usually available in efficient implementations, and compare their rate-distortion performance with JPEG2000, JPEG-XT and H.265/HEVC codecs supporting direct compression of infrared images in 16 bit depth format. A preliminary result shows that two 8 bit H.264/AVC codecs can achieve similar result as 16 bit HEVC codec.
We propose a zero block detection algorithm and architecture in EBCOT. After the
detailed analysis of wavelet coefficients’ precision and distribution in JPEG2000, there are three
main modes of zero coefficients in the wavelet domain, i.e. zero column, zero stripe and zero code
block. And we also discover that the coding information of each bit plane and the corresponding
passes can be obtained simultaneously in the hardware structure. Therefore, bit plane-parallel and
pass-parallel coding with zero detection is proposed, and its VLSI architecture is shown in details.
The analysis and the corresponding software/hardware experimental results show that the
proposed architecture reduces the processing time greatly compared with others.
KEYWORDS: 3D video compression, Video compression, Discrete wavelet transforms, Binary data, Video surveillance, Video, Computer programming, Video coding, Scalable video coding, Wavelets
This paper is dedicated to entropy coding for scalable video compression based on three-dimensional discrete
wavelet transform (3-D DWT). A new simple bit-plane entropy coding of wavelet subband matrices is proposed.
Practical results show that 3-D DWT video codec with proposed entropy coding allows to increase the encoding
speed 2-3 times for the same quality level in comparison with x.264 codec which is one of the fastest software
implementation of H.264/AVC standard.
The paper presents a context-based arithmetic coder's VLSI architecture used in SPIHT
with reduced memory, which is used for high speed real-time applications. For hardware
implementation, a dedicated context model is proposed for the coder. Each context can be
processed in parallel and high speed operators are used for interval calculations. An embedded
register array is used for cumulative frequency update. As a result, the coder can consume one
symbol at each clock cycle. After FPGA synthesis and simulation, the throughput of our coder is
comparable with those of similar hardware architectures used in ASIC technology. Especially, the
memory capacity of the coder is smaller than those of corresponding systems.
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