This method reduces the data path from the counter to the pixel register of the analog-to-digital converter (ADC) from as
many as 10 bits to a single bit. The reduction in data path width is accomplished by using a coded serial data stream
similar to a pseudo random number (PRN) generator. The resulting encoded pixel data is then decoded into a standard
hexadecimal format before storage. The high-speed serial pixel ADC concept is based on the single-slope integrating
pixel ADC architecture. Previous work has described a massively parallel pixel readout of a similar architecture. The
serial ADC connection is similar to the state-of-the art method with the exception that the pixel ADC register is a shift
register and the data path is a single bit. A state-of-the-art individual-pixel ADC uses a single-slope charge integration
converter architecture with integral registers and "one-hot" counters. This implies that parallel data bits are routed among
the counter and the individual on-chip pixel ADC registers. The data path bit-width to the pixel is therefore equivalent to
the pixel ADC bit resolution.
George Yates, Claudine Pena, Thomas McDonald, Robert Gallegos, Dustin Numkena, Bojan Turko, George Ziska, Jacques Millaud, Rick Diaz, John Buckley, Glen Anthony, Takae Araki, Eric Larson
A high frame rate optically shuttered CCD camera for radiometric imaging of transient optical phenomena has been designed and several prototypes fabricated, which are now in evaluation phase. the camera design incorporates stripline geometry image intensifiers for ultra fast image shutters capable of 200ps exposures. The intensifiers are fiber optically coupled to a multiport CCD capable of 75 MHz pixel clocking to achieve 4KHz frame rate for 512 X 512 pixels from simultaneous readout of 16 individual segments of the CCD array. The intensifier, Philips XX1412MH/E03 is generically a Generation II proximity-focused micro channel plate intensifier (MCPII) redesigned for high speed gating by Los Alamos National Laboratory and manufactured by Philips Components. The CCD is a Reticon HSO512 split storage with bi-direcitonal vertical readout architecture. The camera main frame is designed utilizing a multilayer motherboard for transporting CCD video signals and clocks via imbedded stripline buses designed for 100MHz operation. The MCPII gate duration and gain variables are controlled and measured in real time and up-dated for data logging each frame, with 10-bit resolution, selectable either locally or by computer. The camera provides both analog and 10-bit digital video. The camera's architecture, salient design characteristics, and current test data depicting resolution, dynamic range, shutter sequences, and image reconstruction will be presented and discussed.
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