In a joint development program between ASML and Motorola a new set of alignment marks have been designed and tested using the ATHENA off-axis alignment system on the ASML scanner. The new marks were analyzed for improved robustness against varying wafer-processing conditions to verify improved overlay capability and stability. These new marks have been evaluated on a set of dual inlaid-copper short flow wafers, with layer stacks consisting of 180 nm technology generation dielectric materials. Typical process variation has been deliberately introduced as part of the designed experiment to study the performance robustness of the new alignment marks. This paper discusses the new mark design and the theoretical reasons for mark design and/or integration change. Results shown in this paper provide initial feedback as to the viability of new variations of ATHENA alignment marks, specifically the SSPM and VSPM. Included in the results is the investigation to further stabilization of alignment signal strength. New ideas that are currently under development, to increase alignment mark signal strength stability, are discussed.
This paper demonstrates a method of analysis to determine a minimum achievable overlay design rule, for an existing stepper tool set in a high volume manufacturing fab. Overlay parameters and Critical Dimensions are considered in an overlay budget applying a modified algorithm to the evaluation of reticle errors, tool performance, and design rule analysis. The modified algorithm is used to determine the capability of an installed tool set of high NA steppers to meet the aggressive overlay requirements for advanced BiCMOS device performance. Design rule boundaries and tool set capability are thoroughly investigated. Experimental results from lithographic tests are used in a modified algorithm to determine the capability of running with current design rules or requiring a change for manufacturability. The impact of writing reticles to tighter specifications for both Critical Dimensions and pattern placement are considered. This study provides a method for chip designers and process engineers to determine the lithographic capability of an installed tool set where a part will eventually be fabricated. The results demonstrate that design rules demand optimum tool performance for overlay and CD control as well as provide a tool for the evaluation of continuous improvement.
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