As IC dimensions continue to shrink beyond the 22nm node, optical single exposure cannot sustain the resolution
required and various double patterning techniques have become the main stream prior to the availability of EUV
lithography. Among various kinds of double patterning techniques, positive splitting pitch lithography-etch-lithographyetch
(LELE) double patterning is chosen for printing complex foundry circuit designs. Tighter circuit CD and process
margin control in such positive splitting pitch LELE double patterning process becomes increasingly critical especially
for topography issues induced by the 1st mask patterning with the 2nd mask exposure. In this paper, laser parameters,
topography issues with the 2nd mask exposure, and SMO effects on CD performances are described in terms of the
proximity CD portion of the scanner CD budget. Laser parameters, e.g. spectral shape and bandwidth, were input into the
photolithography simulator, Prolith, to calculate their impacts on circuit CD variation. Mask-bias dependent lithographic
performance was calculated and used to illustrate the importance of well-controlled laser performance parameters.
Recommended laser bandwidth, mask bias and topography requirements are proposed, based on simulation results to
ensure that the tight CD control (< 1nm) required for advanced technology node products can be achieved.
Tight circuit CD control in a photolithographic process has become increasingly critical particularly for advanced
process nodes below 32nm, not only because of its impact on device performance but also because the CD control
requirements are approaching the limits of measurement capability. Process stability relies on tight control of every
factor which may impact the photolithographic performance. The variation of circuit CD depends on many factors, for
example, CD uniformity on reticles, focus and dose errors, lens aberrations, partial coherence variation, photoresist
performance and changes in laser spectrum. Laser bandwidth and illumination partial coherence are two significant
contributors to the proximity CD portion of the scanner CD budget. It has been reported that bandwidth can contribute
to as much as 9% of the available CD budget, which is equivalent to ~0.5nm at the 32nm node. In this paper, we are
going to focus on the contributions of key laser parameters e.g. spectral shape and bandwidth, on circuit CD variation for
an advanced node logic device. These key laser parameters will be input into the photolithography simulator, Prolith, to
calculate their impacts on circuit CD variation. Stable though-pitch proximity behavior is one of the critical topics for
foundry products, and will also be described in the paper.
Extreme ultraviolet (EUV) technology has been recognized as the major lithography technology for 22 nm HP and
beyond to fulfill Moore's Law, which predicts that circuit dimensions shrink 70% every 2~3 years in order to achieve
cost down and obtain greater functionality per unit area. EUV source power is one of the key factors in determining the
cost-effectiveness of EUVL compared to other lithography technologies, like double patterning. Only when EUV
power can achieve a certain level, the cost of EUV lithography under high volume manufacturing (HVM) can become
much more competitive than that of double patterning techniques. In this paper, the performance of the first production
Cymer high power laser produced plasma (LPP) EUV source integrated with a 5 sr multi-layer mirror (MLM) collector
and fully integrated debris mitigation will be shown. The latest results on power generation, stable and efficient
collection, and clean transmission of EUV light through the intermediate focus will be presented. The lifetime of the
MLM collector is a critical parameter in the development of extreme ultraviolet LPP lithography sources. Debris
mitigation techniques are used to inhibit reflectivity degradation from deposition of target material, sputtering of the
multilayer coating, and implantation of incident particles, which can reduce the efficiency of the MLM collector during
exposure. The far field images of MLM collector are recorded by intermediate focus metrology with a CCD camera to
determine the reflectivity status of the MLM collector during exposure. The results of these debris mitigation techniques
are compared through multiple-hour EUV exposure. Testing shows cleanliness at the source-scanner interface acceptable
to the limit of detection.
As the process development advances to deep sub-100 nm technology, many new
technologies such as immersion lithography and hyper NA lens design are developed for
the improved on-wafer pattern resolution to meet the technology requirement. During the
early process development such as 45 nm technology, it was not clear that lithography
tool could meet stringent CD variation requirement. Many rules such as fixed poly pitch,
single poly orientation, and dummy poly insertion for diffusion edge transistors were
implemented [1, 2] to ensure that, with designated litho-tool, the CD variation control
could be minimized. These rules generally added layout design complexity and area
penalty. It would be efficient that these rules could be evaluated and properly
implemented with data collected from well-design test structures.
In this work, a set of simple test structures with various dummy poly gate lengths
and numbers of dummy poly gates, and fix-pitch poly gate orientations were
implemented in the process development test vehicles (TV's). Electrical, simulation, and
in-line CD data of these test structures were collected. Analysis of the data and related
design rule optimization and implementation are described. This work helped to optimize and to properly implement the 45 nm gate poly
design rules during early process development for Xilinx FPGA product development.
Control of circuit CD in a photolithographic process has become increasingly important, particularly for those advanced nodes below 45nm because it influences device performances greatly. The variation of circuit CD depends on many factors, for example, CD uniformity on reticles, focus, lens aberrations, partial coherence, photoresist performance and LASER spectral bandwidth. In this paper, we focus on LASER spectral bandwidth effects to reduce circuit CD variation. High-volume products of a leading technology node are examined and a novel LASER control function: Gas Lifetime eXtenstion (GLX) is implemented to obtain stable LASER bandwidth. The LASER bandwidth variation was stabilized by changing laser F2 gas concentration through advanced control algorithm and signal process techniques. Product photo-pattern CD variation and device electrical performances will be examined to confirm the benefits of the LASER bandwidth stabilization.
High NA (1.35) Immersion litho runs into the fundamental limit of printing at 40-45nm half pitch (HP). The next generation EUVL tool is known to be ready not until year 2012. Double patterning (DP) technology has been identified as the extension of optical photolithography technologies to 3xnm and 2xnm half-pitch for the low k1 regime to fill in the gap between Immersion lithography and EUVL. Self Aligned Double Patterning (SADP) Technology utilized mature process technology to reduce risk and faster time to market to support the continuation of Moore's Law of Scaling to reduce the cost/function. SADP uses spacer to do the pitch splitting bypass the conventional double patterning (e.g. Litho-Freeze-Litho-Etch (LFLE), or Litho-Etch-Litho-Etch (LELE)) overlay problem. Having a tight overlay performance is extremely critical for NAND Flash manufacturers to achieve a fast yield ramp in production. This paper describes the challenges and accomplishment of a Line-By-Spacer (LBS) SADP scheme to pattern the 29nm half-pitch NAND Flash STI application. A 193nm Dry lithography was chosen to pattern on top of the amorphous carbon (a-C) film stack. The resist pattern will be transferred on the top a-C core layer follow by spacer deposition and etch to achieve the pitch splitting. Then the spacer will be used to transfer to the bottom a-C universal hardmask. This high selectivity a-C hardmask will be used to transfer the 29nm half-pitch pattern to the STI. Good within wafer CD uniformity (CDU) <2nm and line width roughness (LWR) <2nm for the 29nm half-pitch NAND FLASH STI were demonstrated as the benefits using double amorphous carbon hardmask layers. The relationships among the photoresist CDs, CD trimming , as-deposited spacer film thickness, spacer width and the final STI line/core space/gap space CDs will also be discussed in this paper since patterning is combining both lithography performance with CVD and Etch process performance. Film selection for amorphous carbon and the complete DP hardmask scheme in terms of etching selectivity, optical properties and stress optimization was another key challenge to balance excellent litho alignment signal strength and straight pattern profiles without line bending effects. Etching efforts also played a very important roll to obtain pattern integrality under such a high aspect ratio (> 10) case through the whole SADP process. Finally, cost analysis for 193nm dry lithography SADP will be compared to 193nm Immersion lithography SADP.
Immersion technology is definitely the mainstream lithography technology for NAND FLASH in recent years since
hyper-NA immersion technology drives the resolution limit down to the 40-50 nm half pitch region. Immersion
defectivity and overlay issues are key challenges before introducing immersion technology into mass production. In this
work, both long term immersion defectivity and overlay data, as well as good photoresist performance, show the Nikon
S610C immersion scanner plus LITHIUS i+ cluster is capable of 40-50 nm NAND FLASH mass production. Immersion
defects are classified based on their causes, and no tool specific immersion defects, e.g. bubbles and water marks, were
found in the Nikon S610C plus TEL LITHIUS i+ cluster. Materials-induced immersion defects require more attention to
achieve production-worthy results.
As the semiconductor industry continues to drive towards high volume production at the 50nm technology node and
beyond, there are formidable barriers imposed not only from technical challenges but also from economic challenges
related to controlling overlay tightly enough to meet the strict requirements of a increasingly smaller overlay control
window. In this paper, the authors will show potential sources overlay error for a 50nm node process and detail a
methodology to pinpoint the root cause and an application to help reduce these errors to facilitate the ramp of a new
process technology for high volume DRAM/FLASH manufacturing. In short, based on a series of experiments and
analysis, the authors have identified high-order wafer-level residual component to be the main contribution of the high
residuals with the source attributed to the scanner mix-and-match set. In turn, an overlay control approach using high
order correctables generated from the overlay metrology system and fed through the APC system will be able to
effectively reduce the mix-and-match high residual errors.
A new method to calibrate optical lithography model using a combination of
measured Critical Dimension (CD) data from the standard patterns and product layout
SEM pictures have been developed. The CD data is composed of the measured CDs of
through-pitch line patterns as well as isolated line and isolated space patterns. The SEM
pictures for contour CD calibrations are from the product layouts. The small set of 1-D
CD data is firstly used to calibrate the model. After best one-dimensional (1-D) data
calibration accuracy is achieved, the model is used to predict the contour of the product
layouts where the SEM pictures are taken. The simulated contours are overlaid with the
SEM pictures to identify the mismatch locations. Additional calibration gauges at the
locations are then added to the model to improve the predicted CD accuracy of 2-
dimensional (2-D) patterns such as line-to-tip, tip-to-tip, and corner. In comparison with
the SEM picture CDs, this procedure can be repeated several times until desired accuracy
of the predicted contours is achieved. This method can increase the model's 2-D edge
prediction accuracy and can reduce the amount of CD data required for model calibration.
This calibration method is used to generate the models for lithography process
simulations for Xilinx's 65 nm product developments. Hot spots and out-of-spec OPC
CD locations are identified using the models and later confirmed from in-line data.
A combination of simulation, resist modification and process optimization were used to develop production worthy dry 193nm lithography processes, suitable for the metal trench layers of 65nm node logic devices. The important performance characteristics of a back-end metal trench layer are through-pitch proximity bias, lithographic latitude and ultimate resolution. Simulation results suggested that a moderate annular illumination setting balances proximity bias against resolution at the forbidden pitch, yielding a good overall through-pitch common process window. Resist material optimization through resin, PAG (photo-acid generator) and base quencher modification improves proximity bias and results in excellent lithographic performances of good LER (line edge roughness), low MEF (Mask Error Factor) and wider process latitude. To investigate extendibility to 45nm node applications, the immersion compatibility of the optimized resist with several top coats are reported.
Spectroscopic critical dimension (SCDTM) metrology on line gratings has previously been shown to be a sensitive and useful technique for monitoring lithographic focus and exposure conditions. Line end shortening (LES) effects are sensitive to focus and potentially more sensitive to focus variation than side wall angle or other profile parameters of line gratings. Rectangular line segment structures that exhibit line-end shortening behavior are arranged in a rectangular two-dimensional (2D) array to provide a scatterometry signal sensitive to the profile of the thousands of line ends in the measurement beam spot. Spectroscopic ellipsometry (SE)-based scatterometry measurements were carried out on 2D array targets of rectangular features exposed in a focus-exposure matrix (FEM). The focus and exposure sensitivities of multiple shape parameters were found to be good and uniquely separable. In addition, the side wall angle of the line ends was found to be nearly linearly dependent on focus and provide necessary focus direction information. Focus and exposure can be determined from SCD measurements by applying a model generated to describe the focus-exposure behavior of multiple shape parameters using KLA Tencor's KT Analyzer software. Several different models based on different combinations of shape parameters were evaluated. Focus measurement precision of 3nm 3σ was obtained, which will be useful for lithography processes with tight depth of focus.
In this paper we describe, from the user's point of view, how Inverse Lithography Technology (ILT) differs from Optical Proximity Correction (OPC). We discuss some specifics of ILT at chip-scale. We show simulation and experimental results from 90nm and 65nm semiconductor nodes, comparing results from ILT-generated masks and OPC-generated masks for real-life layouts, in a production environment. In addition, we discuss issues related to complexity and manufacturability of ILT-generated masks.
In this paper, we will demonstrate a novel approach to improve process window prediction capability. The new method, Lithography Manufacturability Check (LMC), will be shown to be capable of predicting wafer level CDs across an entire chip and the lithography process window with a CD accuracy of better than 10nm. The impact of reticle CD error on the weak points also will be discussed. The advantages of LMC for full chip process window analysis as well as the MEEF check to catch process weak points will be shown and the application to real designs will be demonstrated in this paper. LMC and MEEF checks are based on a new lithography model referred to as the Focus Exposure Matrix Model (FEM Model). Using this approach, a single model capable of simulating a complete range of focus and exposure conditions can be generated with minimal effort. Such models will be shown to achieve a predictive accuracy of less than 5nm for device patterns at nominal conditions and less than 10nm across the entire range of process conditions which define the nominal process window. Based on the inspection results of the full chip LMC check, we identify process weak points (with limited process window or excessive sensitivity to mask error) and provide feedback to the front end design stage for pattern correction to maximize the overall process window and increase production manufacturability. The performance and full function of LMC will also be described in this paper.
As the advent of advanced process technology such as 90-nm and below, the design rules become more and more complicated than before. These complicated design rules can guarantee process margin for the most layout environments. However, some layouts have narrow process windows that were still within the design rules. For example, line end layouts in a dense environment would generally have narrower process window than that of the onedimensional (1-D) dense line environment. The dense line end spacing design rule would be larger than that of the 1-D dense line spacing to compensate for the narrow window effect. In this work, an optical simulation software was used to examine an existing 90-nm FPGA product pre-OPC layout for its optical contrast. The optical contrast could correlate to the depth of focus (DOF) process window. Several back end locations were identified with possible narrow DOF windows. From the evaluations of these low contrast patterns, several design for manufacturing (DFM) rules and DRC deck was then developed. This deck
effectively identified the narrow process window layout locations, previously found with the simulation software. These locations were then optimized for the improved DOF windows. Both simulation and in-line data showed that the DOF window was improved after the layout optimization. Product data with optimized layouts also showed the improved yield.
In the post-physical verification space called 'Mask Synthesis' a key component of design-for-manufacturing (DFM), double-exposure based, dark-field, alternating PSM (Alt-PSM) is being increasingly applied at the 90nm node in addition with other mature resolution enhancement techniques (RETs) such as optical proximity correction (OPC) and sub-resolution assist features (SRAF). Several high-performance IC manufacturers already use alt-PSM technology in 65nm production. At 90nm having strong control over the lithography process is a critical component in meeting targeted yield goals. However, implementing alt-PSM in production has been challenging due to several factors such as
phase conflict errors, mask manufacturing, and the increased production cost due to the need for two masks in the process. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a mature, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. With minimum design changes, design houses usually are motivated by higher product performance for the existing designs. What follows is an in-depth review of the motivation to apply alt-PSM on a production FPGA, the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.
In this paper we describe, from the user's point of view, how Inverse Lithography Technology (ILT) differs from Optical Proximity Correction (OPC). We show simulation and experimental results from 90nm and 65nm semiconductor nodes, comparing ILT-generated masks and OPC-generated masks for real-life layouts, in a production environment. In addition, we discuss issues related to complexity and manufacturability of ILT-generated masks.
Tight control of critical dimensions (CDs) of integrated circuit (IC) is required to achieve desired circuit performances, and getting more and more important as the IC CD shrinks. Phenomena and solutions of inter-field and intra-field CD errors have been widely studied for years. One of the well-known intra-field CD errors is so called the developer micro-loading effect due to the different pattern density loadings across the exposure field, in the other words, the more different the pattern density is, the more CD errors it would be expected. Some of the circuit layouts, e.g. thick gate oxide layers of dual gate oxide processes, and gate layers of embedded memory products, have this kind of across field pattern density concerns because of the different pattern density areas. Some researches showed that eliminating the by-products during the development process could reduce the developer micro-loading effect. With a multi-step development process (Puddle-Static Development-Dry-Puddle-Static Development-Rinse/Dry), the by-products can be removed and achieve a better CD uniformity. In this paper, optimization of the first puddle time in the multi-step development process is found to be the most critical to achieve uniform intra-field CDs. The purpose of the first puddle step is not only to remove the by-products but also to control the influence of the by-products to achieve uniform intra-field CDs. Once most of the by-products generated during the whole development process were carried away by the first puddle step, the optimum static Dev. time is needed to obtain the minimum intra-field CD difference. However, different photo-resists with different chemical formulations are expected to have identical optimum puddle time due to different chemical reactions of each by-product species, e.g. i-line PRs vs DUV PRs, or annealing type DUV PRs vs acetel type DUV PRs. These comparisons will be explained in details in this paper. Finally, the source of the by-products during the developer process was also identified to verify the validation of the multi-step developer process.
Lot-to-lot ADI CD data are generally used to tighten the variation of exposure energy of an exposure tool through an APC feedback system. With decreasing device size, the process window of an exposure tool becomes smaller and smaller. Therefore, whether the ADI CD can reveal the real behavior of a scanner or not becomes more and more a critical question, especially for the polysilicon gate layer. CD-SEM has generally been chosen as the metrology tool for this purpose. Because of the limitations of top-down CD-SEMs, an APC system could be easily misled by improper ADI CD data if the CD data were measured on a T-topped photo resist. ArF resist shrinkage and line edge roughness are also traditional causes for improper CD feedback if the user did not operate the CDSEM carefully. Another candidate for this APC application is spectroscopic-ellipsometry-based scatterometry technology, commonly referred to as SpectraCD. In recent studies, SpectraCD was proven to be able to reveal profile variation with excellent stability. The feasibility of improving a CDSEM-based APC system by a SpectraCD-based system in a high-volume manufacturing fab is therefore worthy of study.
This study starts from an analysis of the historical data for the polysilicon ADI CD of a 130 nm product. Two different sets of CD measured from the two different metrology tools were analyzed. In the fab, CDSEM was the metrology tool chosen for the APC feedback. The CD data measured by SpectraCD over a 2 month timeframe were plotted as a CD trend chart of the specific exposure tool. There are several trend-ups and trend-downs observed, even though the overall CD range is small. After a series of analyses, the exposure tool has been proven to be quite stable and the CD data measured by SpectraCD also reveal the real behavior of the exposure tool correctly. The scanner is shown to have been misled by improper CD feedback. In comparison with CDSEM, the linearity of the correlation between ADI and AEI CDs, which represents the consistence of etch bias, can also be improved from 0.4 to 0.8 by SpectraCD. The root causes are still under investigation, but one suspected reason is related to resist profile. All the analysis results will be reported in this paper. The data provided sufficient motivation for switching the APC feedback system of the fab from a CDSEM-based system to a SpectraCD-based system. The results of the new APC system will also be discussed.
Optical resolution limit is one of the concerns for exposure tool selection. ArF lithography tools are the first choice for critical layers of 90 nm node with pitches narrower than 280 nm. However, high cost of ArF tools and photoresists make IC manufacturers try to seek for alternatives. Extension of KrF lithography has been widely discussed. For mass production of 130 nm node, KrF lithography has been pushed hard to achieve 160 nm contact holes with 320 nm pitch. In this paper, printing of via holes with the minimum pitch of 280 nm has been demonstrated with a special designed multi-pole aperture and high NA KrF lithography. With these illumination settings, reasonable process windows through all the pitches can be achieved for mass production of 90 nm node logic devices. Multi-pole illumination aperture settings are critical for balancing through-pitch process margins. Forbidden regions should not be found with optimum multi-pole illumination settings. In other words, the adequate combinations of multi-pole sizes and locations can minimize the forbidden proximity behavior and also keep the aerial imaging contrast balance through all the pitches. Mask bias is another factor to enlarge the common process windows. The process margin depth of focus (DOF) and mask enhanced error factor (MEEF) are investigated with various multi-pole settings and mask biases. Simulation works have been done for fine-tuning of the multi-pole aperture to reduce through pitch MEEF and optimize mask biases.
In 65nm and beyond generations, contact/via patterning is more challenging due to the complexity of manufacturing masks and the weak lithography process window. High NA scanners and suitable illumination can provide the desired resolution and dense pitch. However, there are trade-offs between process window, mask error enhancement factor (MEEF), and proximity effect. Some assistant technology is reported in literature, such as thermal flow, RELACS, SAFIER and sub-resolution assistant features. In this paper, we report a detailed study of the feasibility and limitations of these kinds of methods. Finally, we describe sub-resolution assistant features when used in QUASAR illumination with lower sigma, which have shown great promise to reduce the proximity effect and MEEF to get a larger lithography process window.
Obtaining good post-etching CD uniformity is getting more and more important in advanced processes such as 90 nm, 65 nm, and even 45nm for 300 mm wafers. But process noise greatly impacts the CD uniformity, especially etching bias and metrology noise. To achieve a CD uniformity of below 3 nm for 300 mm post-etch wafers, the metrology noise and process noise must be reduced and compensated for. In this paper, we demonstrate spectroscopic ellipsometry CD with the advantages of high stability and high accuracy to get CD information precisely, and high sensitivity to monitor PEB temperature and exposure energy fine variation in order to compensate for the etching bias.
This study focuses on the feasibility of minimizing the CD uniformity of post-etch wafers by ADI CD compensation for a 300 mm leading-edge fab. Because the CD uniformity of after-development inspection (ADI) wafers from a leading-edge lithographic tool could be in the range of only 3 nm, it is very challenging to reveal the true CD signature of an ADI wafer using a metrology tool. A spectroscopic ellipsometry based metrology tool, SpectraCD, was used in this study. In order to make sure the CD signatures reported by SpectraCD reveal the true behavior of a lithographic tool, the well-published Total Test Repeatability (TTR) test was adopted. In comparison with 3 nm CD uniformity, a 0.2 nm TTR is accurate enough for this study. In addition, from more than 100 wafers produced within a week, the CD signature of ADI wafers is very stable on wafer-to-wafer and lot-to-lot bases. Basically, all the ADI wafers produced from a single post-exposure-bake plate of an exposure tool within a week show very similar CD signatures. The feasibility of reaching a CD uniformity of 3 nm for post-etch wafers will be demonstrated in this study.
The integrated circuit (IC) manufacturing factories have measured overlay with conventional "box-in-box" (BiB) or "frame-in-frame" (FiF) structures for many years. Since UMC played as a roll of world class IC foundry service provider, tighter and tighter alignment accuracy specs need to be achieved from generation to generation to meet any kind of customers' requirement, especially according to International Technology Roadmap for Semiconductors (ITRS) 2003 METROLOGY section1. The process noises resulting from dishing, overlay mark damaging by chemical mechanism polishing (CMP), and the variation of film thickness during deposition are factors which can be very problematic in mark alignment. For example, the conventional "box-in-box" overlay marks could be damaged easily by CMP, because the less local pattern density and wide feature width of the box induce either dishing or asymmetric damages for the measurement targets, which will make the overlay measurement varied and difficult. After Advanced Imaging Metrology (AIM) overlay targets was introduced by KLA-Tencor, studies in the past shown AIM was more robust in overlay metrology than conventional FiF or BiB targets. In this study, the applications of AIM overlay marks under different process conditions will be discussed and compared with the conventional overlay targets. To evaluate the overlay mark performance against process variation on 65nm technology node in 300-mm wafer, three critical layers were chosen in this study. These three layers were Poly, Contact, and Cu-Metal. The overlay targets used for performance comparison were BiB and Non-Segmented AIM (NS AIM) marks. We compared the overlay mark performance on two main areas. The first one was total measurement uncertainty (TMU)3 related items that include Tool Induced Shift (TIS) variability, precision, and matching. The other area is the target robustness against process variations.
Based on the present study AIM mark demonstrated an equal or better performance in the TMU related items under our process conditions. However, when non-optimized tungsten CMP was introduced in the tungsten contact process, due to the dense grating line structure design, we found that AIM mark was much more robust than BiB overlay target.
At the sub 90nm nodes, resolution enhancement techniques (RETs) such as optical proximity correction (OPC), phase-shifting masks (PSM), sub-resolution assist features (SRAF) have become essential steps in the post-physical verification 'Mask Synthesis' process and a key component of design for manufacturing (DFM). Several studies have been conducted and the results have been published on the implication and application of the different types of RETs on mask printability and costs. More specifically, double-exposure-based, dark-field, alternating PSM (Alt-PSM) technology has received lot of attention with respect to the mask manufacturing challenges and its implementation into a production flow, despite its yield and critical dimension (CD) control superiority.
Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a matured, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. What follows is an in-depth review of the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.
Planarization of gap-filling materials for low-k dual damascene processes is getting more and more important due to the photoresist process window shrinking as the pitch and critical dimensions shrink. Defects, especially pattern collapses, will become a serious problem if there is no global planarization for low-k dual damascene processes. IC manufacturers and materials vendors have proposed several ways to improve the global planarization of gap filling, such as using materials with different viscosities, fine tuning gap-filling material coating recipes, and even using optical or chemical treatments to obtain global planarization. The effect of the different conformalities of the first and second coating materials on coating performance will be discussed.
Double Dipole Lithography (DDLä) has been demonstrated to be capable of patterning complex 2D devices patterns. [1,2,3] Due to inherently high aerial image contrast from dipole illumination, we have found that it can meet lithography manufacturing requirements, such as line edge roughness (LER), and critical dimension uniformity (CDU), for the upcoming 65nm node using ArF binary chrome masks. For patterning at k1 below 0.35, DDL is one of the promising resolution enhancement techniques (RET), which can offer process latitudes that are comparable to more costly alternatives such as two-exposure alternating PSM. To use DDL for printing actual IC devices, the original design data must be converted into a "vertical (V)" mask and a "horizontal (H)" mask for the respective X-dipole and Y-dipole exposures. We demonstrated that our model-based DDL mask data processing methodology is capable of converting complex 2D logic and memory designs into dipole-compatible mask layouts. [2,3] Due to the double exposure, stray light must be well controlled to ensure uniform printing across the entire chip. One intuitive solution to minimize stray light is to apply large patches of chrome in the open field areas in order to reduce the background (non-pattern area) exposure level. Unfortunately, this is not viable for a clear-field poly gate mask as it incorporates a positive photoresist process. We developed an innovative and practical background-shielding scheme called sub-resolution grating block (SGB), which is part of the DDL layout conversion method for full-chip application. This technique can effectively minimize the impact of long-range stray light on critical features during the two exposures. Reticles inspection is another important issue for the implementation of DDL technology. In this work, we reported a methodology on how to characterize defects and optimize inspection sensitivity for DDL RET reticles.
Due to the existing problems and delay of 157nm lithography tool, extension of the ArF (193nm) lithography process with resolution enhancement techniques (RET) should be considered for the 65nm generation lithography and beyond. The mature double-exposure lithography process based on dark-field alternating phase-shift mask (PSM) is one of the promising RET candidates, which is proven to be one of the production-ready strong phase-shifting techniques for current and future IC generations. In this paper, poly gate patterning with the minimum pitch of 160nm has been demonstrated with high numeric aperture (NA) and small partial coherence of ArF lithography along with a dark-field alternating PSM. For poly gate patterning of 65nm generation, optimum illumination settings are found for minimum pitch of 160nm. Through-pitch common process windows for gates with 65nm after-development-inspection (ADI) critical dimension (CD) at minimum pitch of 160nm can be reached larger than 0.30um depth of focus (DOF), which can be used for 65nm node production. Through-pitch proximity can be compensated by optical proximity correction (OPC). Line edge roughness (LER) can be improved a little by this dark-field alternating PSM technique. LER is found of strong aerial image contrast dependency. Shifter width is also chosen as optimum value to obtain the largest process windows and minimize the phase conflicts. 193nm Hi-NA or liquid immersion lithography is suggested to push the alternating PSM resolution limitation.
As 6% attenuated phase shift masks (PSM) become commonly used in ArF advanced lithography for the 90nm Technology and mass production to print lines/ spaces as well as contacts, the specification and control of the phase angle and the width of the distribution of phase angles becomes critical to maintain the quality of the lithography process. The influence of the mean phase angle and the width of the distribution of phase angles on the best focus, the through pitch behavior and uniformity of the critical dimension (CD uniformity) has been studied experimentally using a 6% attenuated PSM whose phase angle has been affected by several reticle cleans. The results are consistent with aerial image simulations. Independent specifications for the mean phase angle and the width of the distribution of phase angles have been derived and could be applied for the production of masks in the future.
Ability to predict process behavior under defocus has until now relied on explicit calculations, which while accurate, cannot be realistically used in full-chip optical and process correction strategies due to the long run times. In this work, we have applied a vector model for the optics, and a compact model for the resist development process. Simulations with these models are fast enough to be the basis of full-chip OPC. We verify this strategy with an independent set of measurements, and compare it to current lithographic process fitting strategies. The results indicate that by describing optical processes as accurately as possible, the model accuracy improves over a wider range of defocus conditions when compared to the traditional calibration method. As long as the calibration process successfully decouples optical and resist effects, relatively simple resist models deliver excellent accuracy within the noise level of the metrology measurements. Our data are based on one-dimensional and two-dimensional results using a 193nm system using 0.75 NA and off axis illumination with 6% attenuated phase shift mask. In all cases, a wide variety of sub-resolution assist feature rules were used in order to further test the ability of the models to predict various optical and resist environments.
A small notch or foot existing at the bottom of a polysilicon gate is a common issue for etching processes. The small notch or foot could have a major impact on the length of the polysilicon gate, and the performance of the device would then be impacted significantly, especially for cutting-edge devices. This paper demonstrates the capability of a spectroscopic ellipsometry based profile technology, SpectraCD, as a new metrology tool to monitor polysilicon gate process at 130 nm and 90 nm nodes. Firstly, the capability of SpectraCD as a metrology technology was studied, including dynamic precision and CD correlation. Dynamic precision in the range of 0.1~0.4 nm was demonstrated repeatedly in this study. CD correlation with CDSEM also showed a very linear result. R-squared values of ~0.99 are presented. Secondly, by comparison with images from cross-sectional SEM (XSEM) and TEM (XTEM), it has been proved in this study that SpectraCD can consistently flag different profile excursions of polysilicon gate, e.g., small notching, footing, or undercut. The size of the footing or notch reported by SpectraCD shows a linear correlation with the size extracted from XTEM images, which demonstrates quantitatively SpectraCD capability for detecting profile excursions. Finally, linear correlation between the bottom CD from SpectraCD and the gate lengths determined from electrical test (Lcap) will be presented.
There are many works on extension of KrF lithography for 90 nm logic generation, especially for those back end of line (BEOL) layers. High cost and immaturity of ArF tools and photoresists are the major factors that make IC manufacturers try to seek for the possibility of KrF lithography. For mass production of 130 nm node, KrF lithography has been pushed hard to achieve 160 nm contact holes with 320 nm pitch. However, with pushing KrF lithography further, printing of 140 nm via holes with the minimum pitch of 280 nm was required by the tight 90 nm design rules. Optimizing illumination settings is one way to obtain reasonable process windows through all the pitches for mass production of 90 nm node logic devices, and maintaining exposure tools in good conditions is the other. The control of pattern deformation becomes more and more significant when the critical dimension is drove to the limit. In this paper, oval shaped via holes were found for symmetrical pitch patterns. Lens aberration and synchronization errors of scanners are always the first considerations when pattern deformation happened. But after investigations, improvement of via pattern deformation control has been demonstrated by reducing the low frequency resonance of scanner projection lens. The via deformation is investigated in combination of different scanning and stepping speed of scanner stages, which will cause different amplitude of projection lens resonance. Low frequency region of projection lens resonance spectra showed less amplitude while scanning or stepping speed was slow. Pattern distortion was also reduced as amplitude of low frequency project lens resonance went low. Common process window was then improved due to the elimination of via cd difference between x and y direction. With this improvement, reasonable process window (DOF ~ 0.3 um) can be achieved for mass production of 90 nm devices on KrF lithography tools.
Each new technology node tests the limits of optical lithography. As exposure wavelength is reduced, new imaging techniques are needed to maximize resolution capabilities. The phase shift mask (PSM) is one such technique that is utilized to push the limits of optical lithography. Altering the optical phase of the light that transmits through a photo mask can increase the resolution of a lithographic image significantly. There are several types of phase shift mask and each has a general charateristic in which some transparent area of the mask are given 180° shift in optical phase relative to other nearby transparent areas. The interaction of the aerial images between two features with a relative phase difference of 180° create interference regions that can be used to printed images much closer together and with an increased depth of focus than that of a standard chrome-on-glass mask. An AAPSM is fabricated using a subtractive process in which the quartz substrate is etched to a given depth to produce the desired phase shift. However, intensity imbalances between the etched and non-etched regions due to sidewall scattering can cause resolution, phase and placement errors on the wafer. One method to balance the transmission is 40 nm undercut with 16 nm shifter width bias. Based on our previous study, 40 nm undercut with 16 nm shifter width bias showed an improved balance of intensities between the etched and non-etched regions. The object of this experiment is to implement the AAPSM with 40 nm undercut and 16 nm shifter width bias in SRAM product and the exposure wavelength is 193 nm. The main purpose is to proof the technology of AAPSM with 40 nm undercut and 16 nm shifter width bias in real product. Also verifying all issue of AAPSM in production. In this study, the image imbalance has been corrected via 40 nm undercut and 16 nm shifter width bias, and the DOF of AAPSM for wafer print performance is larger than binary mask. The DOF of AAPSM is about 0.5 μm and the conventional binary mask is 0.3μm.
In our previously published work, we investigated alternating-aperture PSM image intensity imbalance as function of various mask and optical parameters using rigorous electro-magnetic field (EMF) simulations. Results suggested that the imbalance could be effectively compensated through application of an optimized combination of undercut and a constant phase-shifter bias. In the effort of development and implementation of a production-ready image imbalance correction methodology, it is important to validate the accuracy of simulation-based predictions through correlation of results to experimental data. For this purpose, a test reticle containing various mask parameters as variables was designed and manufactured. The experimental data was obtained from SEM measurements of the exposed wafers, and results were compared to rigorous EMF simulation data. Based on results obtained, we propose and validate an image imbalance correction methodology to be implemented within the framework of the PSM - OPC manufacturing flow.
An extended 248nm lithography process with alternating phase-shift masks (PSMs) and etch-trimming techniques has produced 50nm gate critical dimensions (CDs). Well-controlled CD uniformity and line-end edge roughness (LER) are also demonstrated in this work. The primary factor in the improvement of through-pitch proximity bias was phase shifter width. With optimum shifter width, where pitches are greater than 600 nm, a through-pitch proximity bias of less than 10 nm can be obtained. Photoresist also has a significant role in implementing alternating PSMs, requiring high activation energy and suitable thickness. Soft-bake and post-bake temperatures were determined to enlarge the depth-of-focus (DOF). The forbidden pitch effect was enhanced to constrain the common process window after optical proximity correction (OPC) had been implemented. However, proximity bias can be kept constant with changeable diffusion length due to the through-pitch CD profiles, all isolated like. Improvement of through-focus CD at the forbidden pitch was examined by optimizing diffusion length; the common process window can be improved by 25%. All process results, including line-end roughness, DOF, exposure latitude, well-controlled CD uniformity, and through-pitch proximity bias, showed that 248 nm photolithography with alternating phase shifting mask could meet the requirements of 100nm node application.
In this study, 2PSM and 3PSM are implemented to print low- duty-ratio self-aligned contact plugs. The simulation and experimental results demonstrate that 2PSM has larger process windows than 3PSM. One of the advantages of 2PSM is no asymmetric defocus effect, which is caused by the phase difference of 3PSM and reduces the process window of 3PSM. Defocus-dependent shape distortion in the case of 3PSM is not found in the case of 2PSM, either. Different illumination conditions have been investigated to determine the best illumination condition for 2PSM in terms of large common process window besides less x-y distortion. Optimum illumination parameters and suitable scattering bars can minimize pattern distortion.
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