IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification inspections are costly
for many reasons including the capital equipment, system maintenance, and labor costs. In addition, masks typically
remain in the “requal” phase for extended, non-productive periods of time. The overall “requal” cycle time in which
reticles remain non-productive is challenging to control. Shipping schedules can slip when wafer lots are put on hold
until the master critical layer reticle is returned to production. Unfortunately, substituting backup critical layer reticles
can significantly reduce an otherwise tightly controlled process window adversely affecting wafer yields.
One major requal cycle time component is the disposition process of mask inspections containing hundreds of defects.
Not only is precious non-productive time extended by reviewing hundreds of potentially yield-limiting detections, each
additional classification increases the risk of manual review techniques accidentally passing real yield limiting defects.
Even assuming all defects of interest are flagged by operators, how can any person's judgment be confident regarding
lithographic impact of such defects? The time reticles spend away from scanners combined with potential yield loss due
to lithographic uncertainty presents significant cycle time loss and increased production costs
An automatic defect analysis system (ADAS), which has been in fab production for numerous years, has been improved
to handle the new challenges of 14nm node automate reticle defect classification by simulating each defect’s printability
under the intended illumination conditions. In this study, we have created programmed defects on a production 14nm
node critical-layer reticle. These defects have been analyzed with lithographic simulation software and compared to the
results of both AIMS optical simulation and to actual wafer prints.
Persistently shrinking design rules and increasing process complexity require tight control and monitoring of the exposure tool parameters [1, 2]. While control of exposure dose by means of resist single metric measurements is common and widely adopted. Focus assessment and monitoring are usually more difficult to achieve. A diffused method to determine process specific dose and focus conditions is based on plotting Bossung curves from single CD-SEM measurements and choosing the best focus setting to obtain the desired target CD with the widest useful window. With this approach there is no opportunity to build a data flow architecture that can enable continuous focus monitoring on nominal production wafers [3-5]. KLA-Tencor has developed a method to enable in-line monitoring of scanner focus on production wafers by measuring resist profile shapes on grating targets using scatterometry, and analyzing the information using AcuShapeTM and K-T AnalyzerTM software. This methodology is based on a fast and robust determination of best scanner focus by analyzing focus-exposure matrices (FEMs). This paper will demonstrate the KT CDFE and FEM Analysis methods and their application in production environment.
Advanced IC fabs must inspect critical reticles on a frequent basis to ensure high wafer yields. These necessary requalification inspections have traditionally carried high risk and expense. Manually reviewing sometimes hundreds of potentially yield-limiting detections is a very high-risk activity due to the likelihood of human error; the worst of which is the accidental passing of a real, yield-limiting defect. Painfully high cost is incurred as a result, but high cost is also realized on a daily basis while reticles are being manually classified on inspection tools since these tools often remain in a non-productive state during classification. An automatic defect analysis system (ADAS) has been implemented at a 20nm node wafer fab to automate reticle defect classification by simulating each defect’s printability under the intended illumination conditions. In this paper, we have studied and present results showing the positive impact that an automated reticle defect classification system has on the reticle requalification process; specifically to defect classification speed and accuracy. To verify accuracy, detected defects of interest were analyzed with lithographic simulation software and compared to the results of both AIMS™ optical simulation and to actual wafer prints.
The fast pace of MOSFET scaling is accelerating the introduction of smaller technology nodes to
extend CMOS beyond 20nm as required by Moore’s law. To meet these stringent requirements, the
industry is seeing an increase in the number of critical layers per reticle set as it move to lower
technology nodes especially in a high volume manufacturing operation. These requirements are
resulting in reticles with higher feature densities, smaller feature sizes and highly complex Optical
Proximity Correction (OPC), built with using new absorber and pellicle materials. These rapid
changes are leaving a gap in maintaining these reticles in a fab environment, for not only haze control
but also the functionality of the reticle. The industry standard of using wet techniques (which uses
aggressive chemicals, like SPM, and SC1) to repel reticles can result in damage to the sub‐resolution
assist features (SRAF’s), create changes to CD uniformity and have potential for creating defects that
require other means of removal or repair. Also, these wet cleaning methods in the fab environment
can create source for haze growth. Haze can be controlled by: 1) Chemical free (dry) reticle cleaning,
2) In‐line reticle inspection in fab, and 3) Manage the environment where reticles are stored. In this
paper we will discuss a dry technique (chemical free) to remove pellicle adhesive residue from
advanced optical reticles. Samsung Austin Semiconductors (SAS), jointly worked with Eco‐Snow
System (a division of RAVE N.P., Inc.) to evaluate the use of Dry Reactive Gas (DRG) technique to
remove pellicle adhesive residue on reticles. This technique can significantly reduce the impact to the
critical geometry in active array of the reticle, resulting in preserving the reticle performance level
seen at wafer level. The paper will discuss results on the viability of this technique used on advanced
reticles.
Imprint lithography has been included on the ITRS Lithography Roadmap at the 32, 22 and 16 nm nodes. Step and
Flash Imprint Lithography (S-FIL ®) is a unique method that has been designed from the beginning to enable precise
overlay for creating multilevel devices. A photocurable low viscosity monomer is dispensed dropwise to meet the
pattern density requirements of the device, thus enabling imprint patterning with a uniform residual layer across a field
and across entire wafers. Further, S-FIL provides sub-100 nm feature resolution without the significant expense of
multi-element, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it
is critical to address the infrastructure associated with the fabrication of templates.
For sub-32 nm device manufacturing, one of the major technical challenges remains the fabrication of full-field 1x
templates with commercially viable write times. Recent progress in the writing of sub-40 nm patterns using commercial
variable shape e-beam tools and non-chemically amplified resists has demonstrated a very promising route to realizing
these objectives, and in doing so, has considerably strengthened imprint lithography as a competitive manufacturing
technology for the sub 32nm node. Here we report the first imprinting results from sub-40 nm full-field patterns, using
Samsung's current flash memory production device design. The fabrication of the template is discussed and the
resulting critical dimension control and uniformity are discussed, along with image placement results. The imprinting
results are described in terms of CD uniformity, etch results, and overlay.
Imprint lithography has been included on the ITRS Lithography Roadmap at the 32, 22 and 16 nm nodes. Step and
Flash Imprint Lithography (S-FIL (R)) is a unique patterning method that has been designed from the beginning to enable
precise overlay to enable multilevel device fabrication. A photocurable low viscosity resist is dispensed dropwise to
match the pattern density requirements of the device, thus enabling patterning with a uniform residual layer thickness
across a field and across multiple wafers. Further, S-FIL provides sub-50 nm feature resolution without the significant
expense of multi-element projection optics or advanced illumination sources. However, since the technology is 1X, it is
critical to address the infrastructure associated with the fabrication of imprint masks (templates).
For sub-32 nm device manufacturing, one of the major technical challenges remains the fabrication of full-field 1x
imprint masks with commercially viable write times. Recent progress in the writing of sub-40 nm patterns using
commercial variable shape e-beam tools and non-chemically amplified resists has demonstrated a very promising route
to realizing these objectives, and in doing so, has considerably strengthened imprint lithography as a competitive
manufacturing technology for the sub-32nm node. Here we report the first imprinting results from sub-40 nm full-field
patterns, using Samsung's current flash memory production device design. The fabrication of the imprint mask and the
resulting critical dimension control and uniformity are discussed, along with image placement results. The imprinting
results are described in terms of CD uniformity, etch results, and overlay.
The progressive mask defect problem is an industry-wide mask reliability issue. Even if masks are determined to be
clean upon arrival from the mask supplier, some of these masks can show catastrophic defect growth over the course of
production usage in the fab. The categories of defects that cause reticle-quality degradation over time are defined as
progressive defects, commonly known as crystal growth, haze, fungus or precipitate. This progressive defect problem
has been around for more than a decade and was observed at almost every lithographic wavelength. This problem is
especially severe at 193nm lithography. Triggering the increased severity are shorter wavelength lithography - where
the photons are highly energized - and the concurrent transition to 300 mm wafers, which require photomasks to endure
more prolonged exposure as compared to 200 mm wafers. Both embedded phase shift masks (EPSMs) and chrome-on-glass
masks are affected by progressive defects. These defects are generally found on the patterned surface underneath
the pellicle (on clear, half-tone or chrome patterns), as well as on the backside surface of the masks. Past cases have
indicated that this problem mainly starts on the scribes and borders, with emerging semi-transmissive contamination of
~100nm. These defects then propagate into the die area while growing in both size and opaqueness. Compositional
analysis has shown that the majority of these defects are ammonium sulfate. However, since significant effort focused
on the elimination of ammonium sulfate a new trend has emerged. Current studies show severe defect growth consists of
organic contaminants (ammonium oxalate, cyanuric acid etc.) on half-tone edges and on chromium edges. The sources
for progressive defect mechanisms are under investigation, though several candidates have been considered: maskmaking
materials and process residues (mainly ammonium or sulfate ions), the fab environment, or the stepper
environment. Controlling or balancing these sources may help to reduce the frequency at which these defects occur, but
thus far has been unable to eliminate the problem. With each successive device shrink, the resultant changes in
lithographic wavelength and processing within the mask fabrication facility and IC fab disrupt the fine balance among
the above suspected defect sources, resulting in the return of catastrophic progressive defect growth. Due to this
uncertainty, strict mask quality monitoring in the fab is essential. The ideal reticle quality control goal in a fab should be
to detect any nascent progressive defects before they become yield limiting. Hence, the masks should be monitored on
an established frequency that allows problem masks to be removed from production and sent for rework prior to
impacting device performance and fab yield.
Progressive mask defect problem is an industry wide mask reliability issue. During the start of this problem when the defects on masks are just forming and are still non-critical, it is possible to continue to run such a problem mask in production with relatively low risk of yield impact. But when the defects approach more critical state, a decision needs to be made whether to pull the mask out of production to send for clean (repair). As this problem increases on the high-end masks running DUV lithography where masks are expensive, it is in the interest of the fab to sustain these problem masks in production as long as possible and take these out of production only when absolutely necessary; i.e., when the defects have reached such a critical condition on these masks that it will impact the process window. During the course of this technical work, investigation has been done towards understanding the impact of such small progressive defects on process window. It was seen that a small growing defect may not print at the best focus exposure condition, but it can still influence the process window and can shrink it significantly. With the help of a high-resolution direct reticle inspection, early detection of these defects is possible, but fabs are still searching for a way to disposition (make a go / no-go decision) on these defective masks. But it is not an easy task as the impact of these defects will depend on not only their size, but also on their transmission and MEEF. A lithographic detector has been evaluated to see if this can predict the criticality of such progressive mask defects.
DUV lithography has introduced a progressive mask defect growth problem widely known as crystal growth or haze. Even if the incoming mask quality is good, there is no guarantee that the mask will remain clean during its production usage in the wafer fab. These progressive defects must be caught in advance during production in the fabs. The ideal reticle quality control goal should be to detect any nascent progressive defects before they become yield limiting. So a high- resolution mask inspection is absolutely needed, but then the big question is: "how often the fabs need to re-inspect their masks"?
A previous work towards finding a cost effective mask re-qualification frequency was done by Vince Samek et al. of IBM and Dadi Gudmundsson et al. of KLA-Tencor in 1999 [1], but this work was prior to the above mentioned progressive defect problem that industry started to see at a much higher rate during just the last few years.
In this present paper a realistic mask re-qualification frequency model has been developed based on the data from an advanced DRAM fab environment that is using low k1 lithography. Statistical methods are used to analyze mask inspection and product data, which are combined in a stochastic model.
Advanced transistor research requires the patterning of isolated gate feature sizes well below available illumination wavelengths. In this work, we explore the limits of imaging isolated line features using double exposure strong phase shift methods and 248 nm illumination. Fundamental issues such as aerial image size,flare, simple OPC and resist aspect ratio will be addressed. Non-lithographic feature slimming methods such as UV-bake, etch biasing and oxidation will we explored as well. It is desirable that feature slimming processing also reduce line-edge roughness. Using a combination of strong PSM imaging and feature slimming, we have developed processes for the fabrication of sub-25 nm gate features required by our Schottky Barrier transistor device development efforts.
Dark field (i.e. hole and trench layer) lithographic capability is lagging that of bright field. The most common dark field solution utilizes a biased-up, standard 6% attenuated phase shift mask (PSM) with an under-exposure technique to eliminate side lobes. However, this method produces large optical proximity effects and fails to address the huge mask error enhancement factor (MEEF) associated with dark field layers. It also neglects to provide a dark field lithographic solution beyond the 130nm technology node, which must serve two purposes: 1) to increase resolution without reducing depth of focus, and 2) to reduce the MEEF. Previous studies have shown that by increasing the background transmission in dark field applications, a corresponding decrease in the MEEF was observed. Nevertheless, this technique creates background leakage problems not easily solved without an effective opaqueing scheme. This paper will demonstrate the advantages of high transmission lithography with various approaches. By using chromeless dark field scattering bars around contacts for image contrast and chromeless diffraction gratings in the background, high transmission dark field lithography is made possible. This novel layout strategy combined with a new, very high transmission attenuating layer provides a dark field PSM solution that extends 248nm lithography capabilities beyond what was previously anticipated. It is also more manufacturing-friendly in the mask operation due to the absence of tri-tone array features.
The future of mask industry technology is in flux. While the requirements for current and near-term lithographic capability is well understood, advanced lithography options pose a completely new set of challenges to the mask maker. Challenges are not only process and materials related, but also include more fundamental concerns dealing with how to afford the necessary capability development. This paper identifies the issues and attempts to propose solutions to the industry's growing concerns.
This study explores the capability of printing 100 nm contacts through the use of 9% and 15% attenuated phase shift masks and a 0.75 NA 193 nm scanner. The mask designs targeted simultaneous solutions for 100 nm contacts at pitches from 200 nm to 300 nm. The two masks were successfully manufactured from experimental MoSiON embedded-attenuated phase shift mask (EAPSM) blanks. The 100 nm contacts were successfully printed with a depth of focus (DOF) from 0.1-0.7 μm. Overlapping process windows were not achieved but were possible upon adjustment of the mask biases. The observed mask error enhancement factor (MEEF) was approximately 3 for the 220 nm pitch. Side lobe printing was not observed for either mask.
This work involved a demonstration of the infrastructure and the ability of mask-making equipment to produce 9 inch reticles. While the choices for this particular work made the timing and logistics long and complicated, we find that there currently exists adequate infrastructure to create 9 inch reticles and we have used this ability to produce several demonstration quality examples.
There are several different methods for printing contact holes on wafers using optical lithography. A preferred resolution enhancement technique for improved contact hole lithography performance is the embedded attenuated phase shift mask (EAPSM). The EAPSM comes in many flavors and forms, but the current preferred form is a film transmission of 6 percent and a phase shift of 180 degrees relative to the clear fused silica areas. It is important to note that the phase shift and transmission values for the phase shift mask are at the actinic exposure wavelength of the wafer stepper/scanner. That is the mask is designed to have a transmission of 6 percent and phase shift of 180-degrees at 248nm or 193nm, depending on the wafer stepper. The resulting transmission of the phase shift mask at the inspection tool wavelength of 365nm is much higher, and the phase shift of the 365nm radiation is significantly less than at the shorter actinic wavelength. The gray-scaled aerial images that are collected by the mask inspection tool could vary significantly for the same size 2-D feature in the binary mask, the 248nm EAPSM, and the 193nm EAPSM. This is also compounded by the fact that the inspection tool calibrates the background transmission of the phase shift material as 0 percent transmission and calibrates the transmission of the fused silica as 100 percent transmission. When these gray-scaled images are used in an energy flux algorithm for contact area measurement, they can be potentially different for each of the three types of masks used to print contact holes. This paper explores the issues involved in using an off-actinic aerial image as the basis for the AVI method of contact sizing.
The Chromeless Phase Shift Mask (CLM) approach from ASML MaskTools has been developed as an approach to achieve sub-100nm lithography using currently available stepper technology. The technology uses sub-resolution gray-scaled regions of zero-phase and pi-phase quartz on the mask to produce effective feature widths well below 100nm at the wafer. The features on the mask consist entirely of etched and unetched quartz. No features consist of chrome on the mask. The integration of this type of phase shift mask technology into the photomask-manufacturing environment requires that the mask manufacturer be able to inspect the mask for defects in the quartz. The Defect Sensitivity Monitor (DSM) pattern was used to construct a CLM mask. The mask was inspected using commercially available inspection platforms, and the resulting inspection capability is reported.
Recently a new mask qualification concept is getting more and more attention. Mask makers are challenged to meet mask and defect specifications of 130 and 100-nm technology node. This means very tight specifications, which usually lead to long mask delivery times. A main factor in the mask making process is mask inspection and repair. The mask repair cycle is not only time-consuming, but also bears the danger of damaging a mask. At the same time, when investigating defect printability, it is getting clear that a lot of today detected defects do not affect wafer-printing results at all. The concept Inspect all - Repair only what prints is introduced. In this paper a study comparing different defect classification methods and their impact on mask repair cycle time is presented.
This paper examines the effects of mask printability of various OPC defect types on a MoSi APSM mask using an MSM-100 AIMS tool operating at 248nm as a printability prediction tool. Printability analysis will be used to address differences in intensity, image capture wavelength, defocus, defect size, type, and placement on two substrate materials. Defect correlation to photomask CD error, aerial image intensity error, and MEEF on high-end KrF photomasks will also be studied.
As photomask critical dimensions extend well into the submicron range, optical measurement techniques are approaching the end of their useful life. While offering advantages of being nondestructive, relatively fast, and very precise, optical measurement tools may have accuracy problems due to diffraction. Linearity between measured and actual values is typically lost due to interference, resonance, and shadowing effects even before the diffraction limit is reached. In addition, standards for submicron features do not exist for optical tools. These limitations have given rise to using a Scanning Electron Microscope (SEM) for reticle dimension measurement. Another complication is that no NIST standard exists for chromium photomask dimensions. A CD SEM must therefore be calibrated to some other trusted standard or measurement method. A Stylus NanoProfilometer (SNP) has better inherent resolution than a SEM and was chosen as the standard measurement instrument for both CD SEM and optical tool metrology. This paper describes the cross-calibration of the Leica LWM-250 (white light) optical metrology tool and the KLA-Tencor 8100XP-R CD SEM, with reference to a Surface Interface SNP9000. The primary motivation was to define the usable ranges of both SEM and optical CD measurement systems, allowing for flexible implementation into a photomask manufacturing environment.
The manufacturing of advanced reticles for deep UV steppers has stressed the mask industry's writing, processing, inspection and repair capabilities. Meeting technology demands has been especially arduous for reticle defect inspection with the rapid evolution of both novel PSM materials and OPC geometries. Also, the switch to a 4x- reduction ratio and every-lower k1 wafer lithography has resulted in increased overall defect printability. To respond to these challenges, a new reticle inspection system with laser UV imaging has been evaluated and shown to achieve mask defect sensitivity of 150 nm and below on DUV EA-PSM and OPC masks.
As semiconductor lithography wavelength decreases, pellicle quality becomes more crucial. Previously unprintable membrane defects are now more susceptible to printing, and pellicle film transmission variation may cause nonuniformity in printed feature size. Globally, five companies manufacture DUV film pellicles: DuPont, Exion, Mitsui, MLI, and Shinetsu. A report comparing these vendors' DUV pellicles is presented here. Each vendor provided ten 248 nm pellicles to be evaluated. Pellicle properties evaluated, in order of importance to several semiconductor manufacturers, were transmission uniformity, membrane cleanliness, frame cleanliness, membrane transmission (both on- and off-axis), adhesive uniformity/integrity, and frame width uniformity. Transmission properties were measured with a single beam spectrometer. Frame cleanliness, frame width uniformity, and adhesive integrity were inspected with a micrometer-stage microscope. Visual frame and membrane particle inspections were performed with a high intensity light followed by an automatic, laser-scattering particle inspection tool. None of the vendors passed the requirements provided by semiconductor manufacturers. Deficiencies were observed in membrane transmission, frame and membrane cleanliness, and adhesive integrity.
For obvious cost reasons, semiconductor manufacturers are constantly striving to produce ever smaller wafer geometries with the current installed base of wafer steppers. Many techniques have been used successfully to 'squeeze' more resolution from these steppers than was once thought possible. Wafers processed using non-aggressive k1 factors provided a linear correlation between mask and wafer feature sizes. However, it has been shown that pushing k1 factors to very low levels causes a nonlinear response between changes in photomask and wafer critical dimension. This non-linearity demands extremely tight photomask CD control specifications. Total CD errors 50nm and smaller can cause unacceptable wafer CD variation. In this paper, defect sensitivity and false detection performance of a new advanced line measurement algorithm was tested. The test vehicles included both an industry standard and a custom designed programmed defect test mask. In addition, production masks with naturally occurring localized CD errors that caused wafer pattern bridging were analyzed. This new experimental algorithm has shown localized CD error detection of <EQ 100 nm reticle defects.
For obvious cost reasons, semiconductor manufacturers are constantly striving to produce ever smaller wafer geometries with the current installed base of wafer steppers. Many techniques (phase shifting, optical proximity correction, etc.) have been used successfully to 'squeeze' more resolution from these steppers than was once thought possible. Wafers processed using non-aggressive k1 factors provided a linear correlation between mask and wafer feature sizes. However, it has been shown that pushing k1 factors to very low levels causes a nonlinear response between changes in photomask and wafer critical dimension. This non-linearity demands extremely tight photomask CD control specifications. Total CD errors 50 nm and smaller can cause unacceptable wafer CD variation. Current high end reticle manufacturers are capable of meeting a total CD uniformity specification of approximately 40 nm as measured by sampling strategies using optical metrology tools. These tools are very useful for detecting macro changes in CD; however, they will only detect a localized error if it happens to occur precisely at the point of measurement. In contrast, a pattern inspection system employing a linewidth measurement algorithm can ensure detection of all localized errors within the detection and review capability of the system. The problem with reticle CD error detection capability is that there is a large discrepancy between currently available detection of greater than or equal to 150 nm and required detection of less than or equal to 50 nm necessary for proper wafer functionality at low k1 lithography. In this paper, defect sensitivity and false detection performance of a new advanced line measurement algorithm was tested. The test vehicles included both an industry standard and a custom designed programmed defect test mask. In addition, production masks with naturally occurring localized CD errors that caused wafer pattern bridging were analyzed. This new experimental algorithm has shown localized CD error detection of less than or equal to 100 nm reticle defects.
For years equipment suppliers have opened their doors to evaluations by potential customers. Unfortunately, the only feedback a supplier received concerning its performance was a purchase order (or the lack of one). Neither was there any benchmarking against other suppliers' results to identify niche areas or spark necessary tool improvement programs. The result was an industry where new tool development projects ran the risk of being dictated by conjecture and assumption rather than a more empirical approach. This paper presents a method by which reticle inspection tools can be characterized more comprehensively. While grounded in common sense, some of the techniques used were considered quite unorthodox. By consulting the equipment supplier as to which test vehicles might best demonstrate its tool capability or might expose a weakness in the competitor's tool, topics that the customer might not otherwise have thought of were covered in the evaluation. Securing permission to feed back comprehensive results to all suppliers also guaranteed future focus on critical issues and limited development activities to only those deemed value-added by the customer. In addition, specific test battery topics were derived from consultations with semiconductor customers. The intent was to understand which reticle patterns and defect types were critical to the end user. The expected outcome after this type of evaluation is a quantified performance benchmark which facilitates industry-wide reticle inspection capability improvement over a shorter period of time.
For obvious cost reasons, semiconductor manufacturers are constantly striving to produce ever smaller wafer geometries with the current installed base of wafer steppers. Many techniques (phase shifting, optical proximity correction, etc.) have been used successfully to 'squeeze' more resolution from these steppers than was once thought possible. Wafers processed using non-aggressive k1 factors provided a linear correlation between mask and wafer feature sizes. However, it has been shown that pushing k1 factors to very low levels causes a nonlinear response between changes in photomask and wafer critical dimension. This non-linearity demands extremely tight photomask CD control specifications. Total CD errors 50 nm and smaller can cause unacceptable wafer CD variation. Current high end reticle manufacturers are capable of meeting a total CD uniformity specification of approximately 40 nm as measured by sampling strategies using optical metrology tools. These tools are very useful for detecting macro changes in CD; however, they will only detect a localized error if it happens to occur precisely at the point of measurement. In contrast, a pattern inspection system employing a linewidth measurement algorithm can ensure detection of all localized errors within the detection and review capability of the system. The problem with reticle CD error detection capability is that there is a large discrepancy between currently available detection of greater than or equal to 150 nm and required detection of less than or equal to 50 nm necessary for proper wafer functionality at low k1 lithography. In this paper, defect sensitivity and false detection performance of a new advanced line measurement algorithm was tested. The test vehicles included both an industry standard and a custom designed programed defect test mask. In addition, production masks with naturally occurring localized CD errors that caused wafer pattern bridging were analyzed. This new experimental algorithm has shown localized CD error detection of less than or equal to 100 nm reticle defects.
As wafer fab technology proceeds into smaller images over larger field sizes, there is a need for tighter critical dimension (CD) uniformity and smaller allowable defect sizes. The maskmaker is required to reduce these sources of error as much as possible at the reticle level. As the lithography and process contributions are reduced, contribution from the mask blank itself becomes significant. Selection of the best vendor for optimum CD and defect performance becomes critical. Unfortunately, the best vendor for CD uniformity may not be the best for defect density on certain product types, and vice versa. An additional complication is that the most critical specifications are required over larger areas of 6 multiplied by .250 substrates which have not yet been optimized by blank suppliers.
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