VLSI-Based Systolic Architecture For Fast Gaussian Convolution

A. Giordano; M. Maresca; G. Sandini; T. Vernazza

doi:10.1117/12.7974023

1 January 1987 VLSI-Based Systolic Architecture For Fast Gaussian Convolution

A. Giordano, M. Maresca, G. Sandini, T. Vernazza

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Optical Engineering, Vol. 26, Issue 1, 260163 (January 1987). https://doi.org/10.1117/12.7974023

Abstract

This paper deals with an algorithm-driven architecture devoted to fast edge detection. The architecture has been specifically designed to process large convolution masks in a pyramidal (multiresolution) scheme. The basic element of the convolution board is a programmable VLSI component. Several identical components can be connected in a virtually systolic structure in order to achieve the desired throughput rate. A distinctive feature of the system is the multiple-resolution capability of the convolver board. The number of convolver boards hosted by a multiple bus vision machine can be selected to achieve a parallel multiple-resolution operation. The main application of the proposed architecture is for fast edge detection based on the extraction of the zero crossings of Gaussian filtered images. The paper is divided into two sections: the first presents results of numerical simulations, showing the accuracy of this edge-detection technique applied to convolved images in a pyramidal structure; the second presents the systolic architecture implementing the algorithm.

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A. Giordano, M. Maresca, G. Sandini, and T. Vernazza "VLSI-Based Systolic Architecture For Fast Gaussian Convolution," Optical Engineering 26(1), 260163 (1 January 1987). https://doi.org/10.1117/12.7974023

Published: 1 January 1987

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