With the multiple patterning schemes and recent introduction of EUV lithography, there is a clear need to fully characterize the edge placement error (EPE) budget in the technology development, and if this information is available in-line, use this information for process control. This methodology has been currently applied to the EUV characterization where the overlay (OVL) and local linewidth roughness (LWR) variations contribute the most to the EPE budget. We describe EPE metrology techniques based on design for inspection™ (DFI) methodology, with non-contact electrical measurements of spatial interactions between integrated circuit (IC) elements created with different patterning and manufacturing steps. Specially designed sub-micron scale test structures are placed within the product die (in place of the filler cells and dummy fill without any area penalty), as well as in the scribe lines, which allows for the EPE monitoring with sub-design rule designs. All DFI structures are tested with a custom (designed and manufactured by PDF) eBeam voltage contrast tool with a very high speed and sub-nm resolution. This methodology has been currently applied to the EUV characterization where the OVL and local LWR variations contribute the most to the EPE budget. In this work, we describe and illustrate the DFI methodology application for the EPE and process window characterization and control.