Summary and Future Trends of the 3D IC Process

doi:10.1117/3.2234473.ch4

Book: 3D IC Devices, Technologies, and Manufacturing

Author(s): Hong Xiao

Published: 2016

https://doi.org/10.1117/3.2234473.ch4

Author Affiliations +

Abstract

In the so-called “good old days,” traditional scaling - which scaled the feature size of MOSFETs, such as gate length L, gate width W, and, more importantly, the gate oxide thickness tox - could reduce the IC manufacturing cost, improve device performance, and reduce power consumption. Table 4.1 shows the relationship between the scaling parameters and scaling factor a. The table shows that whenW, L, tox, and V scale down by a factor of 2 (a = 2), the MOSFET can run twice as fast with only one-fourth of the power consumption. If W, L, and tox scale down by a factor of 2 while the voltage V stays unchanged, the device can be four times faster with half of the power consumption. During that era, any pattern on a photomask could be printed on the wafer surface with a high degree of fidelity, albeit with some corner rounding. Those “golden days” of scaling ended after the introduction of the 130-nm technology node, when the gate oxide thickness could be scaled down no further due to tunneling-induced leakage.