Heterostructures for low-power logic and memory devices

Deep Jariwala

doi:10.1117/12.2675677

5 October 2023 Heterostructures for low-power logic and memory devices

Deep Jariwala

Proceedings Volume PC12651, Low-Dimensional Materials and Devices 2023; PC1265104 (2023) https://doi.org/10.1117/12.2675677
Event: SPIE Nanoscience + Engineering, 2023, San Diego, California, United States

Abstract

The isolation of a growing number of two-dimensional (2D) materials has inspired worldwide efforts to integrate distinct 2D materials into van der Waals (vdW) heterostructures. While a tremendous amount of research activity has occurred in assembling disparate 2D materials into “all-2D” van der Waals heterostructures and making outstanding progress on fundamental studies, practical applications of 2D materials will require a broader integration strategy. I will present our ongoing and recent work on integration of 2D materials with 3D electronic materials to realize logic switches and memory devices with novel functionality that can potentially augment the performance and functionality of Silicon technology. First, I will present our recent work on gate-tunable diode and tunnel junction devices based on integration of 2D chalcogenides with Si and GaN. Following this I will present our recent work on non-volatile memories based on Ferroelectric Field Effect Transistors (FE-FETs) made using a heterostructure of MoS2/AlScN, and also introduce our work on Ferroelectric Diode (FeD) devices also based on thin AlScN. In addition, I will also present how FeDs provide a unique advantage in compute-in-memory (CIM) architectures for efficient storage, search as well as hardware implementation of neural networks. I will conclude by providing a broad and optimistic outlook for integration of novel materials and devices in future classical computing chips.

Conference Presentation

Citation Download Citation

Deep Jariwala "Heterostructures for low-power logic and memory devices", Proc. SPIE PC12651, Low-Dimensional Materials and Devices 2023, PC1265104 (5 October 2023); https://doi.org/10.1117/12.2675677

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KEYWORDS

Heterojunctions

2D materials

Logic

Logic devices

Silicon

Field effect transistors

Gallium nitride

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