Paper
24 March 2016 Study of correlation between overlay and displacement measured by Coherent Gradient Sensing (CGS) interferometry
Author Affiliations +
Abstract
Within the semiconductor lithographic process, alignment control is one of the most critical considerations. In order to realize high device performance, semiconductor technology is approaching the 10 nm design rule, which requires progressively smaller overlay budgets. Simultaneously, structures are expanding in the 3rd dimension, thereby increasing the potential for inter-layer distortion. For these reasons, device patterning is becoming increasingly difficult as the portion of the overlay budget attributed to process-induced variation increases. After lithography, overlay gives valuable feedback to the lithography tool; however overlay measurements typically have limited density, especially at the wafer edge, due to throughput considerations. Moreover, since overlay is measured after lithography, it can only react to, but not predict the process-induced overlay.

This study is a joint investigation in a high-volume manufacturing environment of the portion of overlay associated with displacement induced by a single process across many chambers. Displacement measurements are measured by Coherent Gradient Sensing (CGS) interferometry, which generates high-density displacement maps (>3 million points on a 300 mm wafer) such that the stresses induced die-by-die and process-by-process can be tracked in detail. The results indicate the relationship between displacement and overlay shows the ability to forecast overlay values before the lithographic process. Details of the correlation including overlay/displacement range, and lot-to-lot displacement variability are considered.
© (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jeffrey Mileham, Yasushi Tanaka, Doug Anberg, David M. Owen, Byoung-Ho Lee, and Eric Bouche "Study of correlation between overlay and displacement measured by Coherent Gradient Sensing (CGS) interferometry", Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography XXX, 97782W (24 March 2016); https://doi.org/10.1117/12.2220531
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KEYWORDS
Semiconducting wafers

Overlay metrology

Lithography

Distortion

Data modeling

Scanners

Interferometry

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