Paper
18 March 2016 EUV process establishment through litho and etch for N7 node
Yuhei Kuwahara, Shinichiro Kawakami, Minoru Kubota, Koichi Matsunaga, Kathleen Nafus, Philippe Foubert, Ming Mao
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Abstract
Extreme ultraviolet lithography (EUVL) technology is steadily reaching high volume manufacturing for 16nm half pitch node and beyond. However, some challenges, for example scanner availability and resist performance (resolution, CD uniformity (CDU), LWR, etch behavior and so on) are remaining. Advance EUV patterning on the ASML NXE:3300/ CLEAN TRACK LITHIUS Pro Z- EUV litho cluster is launched at imec, allowing for finer pitch patterns for L/S and CH. Tokyo Electron Ltd. and imec are continuously collabo rating to develop manufacturing quality POR processes for NXE:3300. TEL’s technologies to enhance CDU, defectivity and LWR/LER can improve patterning performance. The patterning is characterized and optimized in both litho and etch for a more complete understanding of the final patterning performance. This paper reports on post-litho CDU improvement by litho process optimization and also post-etch LWR reduction by litho and etch process optimization.
© (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yuhei Kuwahara, Shinichiro Kawakami, Minoru Kubota, Koichi Matsunaga, Kathleen Nafus, Philippe Foubert, and Ming Mao "EUV process establishment through litho and etch for N7 node", Proc. SPIE 9776, Extreme Ultraviolet (EUV) Lithography VII, 97760C (18 March 2016); https://doi.org/10.1117/12.2218885
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KEYWORDS
Etching

Line width roughness

Semiconducting wafers

Extreme ultraviolet

Plasma

Optical lithography

Extreme ultraviolet lithography

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