Full chip two-layer CD and overlay process window analysis

Rachit Gupta; Shumay Shang; John Sturtevant

doi:10.1117/12.2086368

18 March 2015 Full chip two-layer CD and overlay process window analysis

Rachit Gupta, Shumay Shang, John Sturtevant

Proceedings Volume 9427, Design-Process-Technology Co-optimization for Manufacturability IX; 94270H (2015) https://doi.org/10.1117/12.2086368
Event: SPIE Advanced Lithography, 2015, San Jose, California, United States

Abstract

In-line CD and overlay metrology specifications are typically established by starting with design rules and making certain assumptions about error distributions which might be encountered in manufacturing. Lot disposition criteria in photo metrology (rework or pass to etch) are set assuming worst case assumptions for CD and overlay respectively. For example poly to active overlay specs start with poly endcap design rules and make assumptions about active and poly lot average and across lot CDs, and incorporate general knowledge about poly line end rounding to ensure that leakage current is maintained within specification. There is an opportunity to go beyond generalized guard band design rules to full-chip, design-specific, model-based exploration of worst case layout locations. Such an approach can leverage not only the above mentioned coupling of CD and overlay errors, but can interrogate all layout configurations for both layers to help determine lot-specific, design-specific CD and overlay dispositioning criteria for the fab. Such an approach can elucidate whether for a specific design layout there exist asymmetries in the response to misalignment which might be exploited in manufacturing. This paper will investigate an example of two-layer model-based analysis of CD and overlay errors. It is shown, somewhat non-intuitively, that there can be small preferred misalignment asymmetries which should be respected to protect yield. We will show this relationship for via-metal overlap. We additionally present a new method of displaying edge placement process window variability, akin to traditional CD process window analysis.

Citation Download Citation

Rachit Gupta, Shumay Shang, and John Sturtevant "Full chip two-layer CD and overlay process window analysis", Proc. SPIE 9427, Design-Process-Technology Co-optimization for Manufacturability IX, 94270H (18 March 2015); https://doi.org/10.1117/12.2086368

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