FPGA implementation of a software-defined radar processor

Hernan Suarez; Yan Rockee Zhang

doi:10.1117/12.2016034

31 May 2013 FPGA implementation of a software-defined radar processor

Hernan Suarez, Yan Rockee Zhang

Proceedings Volume 8714, Radar Sensor Technology XVII; 871403 (2013) https://doi.org/10.1117/12.2016034
Event: SPIE Defense, Security, and Sensing, 2013, Baltimore, Maryland, United States

Abstract

A unified digital pulse compression processor is introduced as a radar-application-specific-processor (RASP) architecture for the next generation of adaptive radar. Based on traditional pulse compression matched filter and correlation receiver, the processor integrates specific designs to handle waveform diversities, which includes random noise waveforms, as well as digital transceiver self-reconfiguration for adaptive radars. Initial prototype of this processor is implemented with the latest Xilinx FPGA device and tested with an RF spaceborne radar transceiver testbed. Initial validation results show the effectiveness of real-time processing and engineering concepts.

Citation Download Citation

Hernan Suarez and Yan Rockee Zhang "FPGA implementation of a software-defined radar processor", Proc. SPIE 8714, Radar Sensor Technology XVII, 871403 (31 May 2013); https://doi.org/10.1117/12.2016034

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