Extending analog design scaling to sub-wavelength lithography: co-optimization of RET and photomasks

Ashesh Parikh; Siew Dorris; Tom Smelko; Walter Walbrick; Pushpa Mahalingam; John Arch; Kent Green; Vishal Garg; Peter Buck; Craig West

doi:10.1117/12.877487

4 April 2011 Extending analog design scaling to sub-wavelength lithography: co-optimization of RET and photomasks

Ashesh Parikh, Siew Dorris, Tom Smelko, Walter Walbrick, Pushpa Mahalingam, John Arch, Kent Green, Vishal Garg, Peter Buck, Craig West

Author Affiliations +

Proceedings Volume 7974, Design for Manufacturability through Design-Process Integration V; 79740N (2011) https://doi.org/10.1117/12.877487
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States

Abstract

The mask requirements for 110nm half-node BiCMOS process were analyzed with the goal to meet customer needs at lower cost and shorter cycle times. The key differentiating features for this technology were high density CMOS libraries along with high-power Bipolar, LDMOS and DECMOS components. The high voltage components were characterized by transistors that formed cylindrical junctions. The presence of curved features in the data is particularly detrimental to the write time on a 50KeV vector mask writer. The mask write times have a direct impact on both mask cost and cycle time. Design rules also permit rectangular or stretched contacts to allow conductance of high currents. To meet customer needs but still manage the computational lithography overhead as well as the patterning process performance, this process was evaluated in terms of computational lithography and photomask co-optimization for the base-line 50KeV vector and laser mask-writers. Due to the differences in imaging and processing of the different mask writing systems, comparative analysis of critical dimension (CD) performance both in terms of linearity and pitch was done. Differences in imaging on silicon due to mask fidelity were also expected and characterized. The required changes in OPC necessary to switch to the new mask process were analyzed.

Citation Download Citation

Ashesh Parikh, Siew Dorris, Tom Smelko, Walter Walbrick, Pushpa Mahalingam, John Arch, Kent Green, Vishal Garg, Peter Buck, and Craig West "Extending analog design scaling to sub-wavelength lithography: co-optimization of RET and photomasks", Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 79740N (4 April 2011); https://doi.org/10.1117/12.877487

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available