Paper
20 April 2011 High-precision edge-roughness measurement of transistor gates using three-dimensional electron microscopy combined with marker-assisted image alignment
Shiano Ono, Miyuki Yamane, Mitsuo Ogasawara, Akira Katakami, Jiro Yugami, Masanari Koguchi, Hiroyuki Shinada, Hiroshi Kakibayashi, Kazuto Ikeda, Yuzuru Ohji
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Abstract
We have improved both the spatial resolution and precision of three-dimensional (3D) electron microscopy, which is based on conventional scanning transmission electron microscopy (STEM), by using a micro-pillar specimen together with a 3D analysis holder, and by introducing marker-assisted image alignment prior to 3D reconstruction. Our 3D STEM measurement of aggressively scaled metal-oxide-semiconductor (MOS) gate structures not only successfully showed the z-axis positional dependence of gate-edge profiles and edge-roughness profiles such as line edge roughness (LER) and line width roughness (LWR), but also revealed uniformity of each layer of which the gate structure was composed. Such observations are very important in controlling future device characteristics, but are difficult to obtain using other measurement techniques.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Shiano Ono, Miyuki Yamane, Mitsuo Ogasawara, Akira Katakami, Jiro Yugami, Masanari Koguchi, Hiroyuki Shinada, Hiroshi Kakibayashi, Kazuto Ikeda, and Yuzuru Ohji "High-precision edge-roughness measurement of transistor gates using three-dimensional electron microscopy combined with marker-assisted image alignment", Proc. SPIE 7971, Metrology, Inspection, and Process Control for Microlithography XXV, 79710M (20 April 2011); https://doi.org/10.1117/12.878949
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KEYWORDS
3D image reconstruction

3D image processing

Scanning transmission electron microscopy

Tin

3D metrology

Line width roughness

Line edge roughness

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