Foundry verification of IP and incoming designs for manufacturing variability

Li-Fu Chang; Julia Fu; Josh Yang; Elain Zou; Philippe Hurat; Nishath Verghese; Hua Ding

doi:10.1117/12.848018

2 April 2010 Foundry verification of IP and incoming designs for manufacturing variability

Li-Fu Chang, Julia Fu, Josh Yang, Elain Zou, Philippe Hurat, Nishath Verghese, Hua Ding

Proceedings Volume 7641, Design for Manufacturability through Design-Process Integration IV; 76410F (2010) https://doi.org/10.1117/12.848018
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

With process technologies advancing to 65nm, 45nm, and below, device timing uncertainty due to lithography and other process variations has easily exceeded 50% and is still growing. In this paper, we present the development of a variability methodology, its correlation with silicon and application to cell and full-chip design verification and optimization. We describe both a methodology for variability analysis of standard cells and a full-chip screening methodology to identify potential chip variability excursions. This methodology relies on model-based analysis and integrates with our existing design-to-manufacturing flow. Based on silicon measurement data of one of our 65nm cell libraries, this methodology has achieved significant improvement in accuracy of estimating timing variations compared to a traditional rule-based method.

Citation Download Citation

Li-Fu Chang, Julia Fu, Josh Yang, Elain Zou, Philippe Hurat, Nishath Verghese, and Hua Ding "Foundry verification of IP and incoming designs for manufacturing variability", Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 76410F (2 April 2010); https://doi.org/10.1117/12.848018

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