IR microscopy as an early electrical yield indicator in bonded wafer pairs used for 3D integration

Andrew C. Rudack; Pratibha Singh; J. Christopher Taylor; Vadim Mashevsky

doi:10.1117/12.848400

1 April 2010 IR microscopy as an early electrical yield indicator in bonded wafer pairs used for 3D integration

Andrew C. Rudack, Pratibha Singh, J. Christopher Taylor, Vadim Mashevsky

Proceedings Volume 7638, Metrology, Inspection, and Process Control for Microlithography XXIV; 763815 (2010) https://doi.org/10.1117/12.848400
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

Microscopy of 3D interconnect structures is challenged by the opaque nature of silicon. Infrared (IR) microscopy provides a way of "looking" through silicon where microscopes based on visible wavelengths fail. Perhaps the most prevalent application of IR microscopes in 3D manufacturing is imaging sub-surface features at the interface of a bonded wafer pair. The ability to see through silicon using IR microscopes enables a variety of metrology techniques, including the overlay of circuit layers (e.g., metal 2 to via). IR microscopy is a non-destructive technique and, as such, it is an ideal candidate for in-line metrology for the bonded wafer pairs required for 3D interconnects. This paper reviews overlay metrology capability for an IR microscope. The ability to measure the overlay of bonded wafer pairs according to the 2009 International Technology Roadmap for Semiconductors (ITRS) is demonstrated. Overlay tolerances for a variety of copper interconnect test structures is predicted based on electrical designs, and overlay results are compared to electrical test results. The use of IR microscopy as an early indicator of electrical yield is clearly demonstrated.

Citation Download Citation

Andrew C. Rudack, Pratibha Singh, J. Christopher Taylor, and Vadim Mashevsky "IR microscopy as an early electrical yield indicator in bonded wafer pairs used for 3D integration", Proc. SPIE 7638, Metrology, Inspection, and Process Control for Microlithography XXIV, 763815 (1 April 2010); https://doi.org/10.1117/12.848400

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