Paper
11 December 2009 Implementation of double patterning process toward 22-nm node
Hidetami Yaegashi, Eiichi Nisimura, Kazuhide Hasebe, Tetsu Kawasaki, Masato Kushibiki, Arisa Hara, Shoichi Yamauchi, Sakurako Natori, Nakajima Shigeru, Hiroki Murakami, Kazuo Yabe, Satoru Shimura, Fumiko Iwao, Kenichi Oyama
Author Affiliations +
Proceedings Volume 7520, Lithography Asia 2009; 75201E (2009) https://doi.org/10.1117/12.839826
Event: SPIE Lithography Asia, 2009, Taipei, Taiwan
Abstract
In the field of photolithography, a variety of resolution enhancement techniques (RETs) are being applied under the mainstream technology of 193-mm water-based immersion lithography. The resolution performance of photoresist, however, is limited at 40 nm. Double patterning (DP) is considered to be an effective technology for overcoming this limiting resolution. Many double-patterning techniques have come to be researched such as litho-etch-litho-etch (LELE), litho-litho-etch (LLE), and self-aligned spacer DP, but as the pattern-splitting type of double patterning requires high overlay accuracy in exposure equipment, the self-aligned type of double patterning has become the main approach. This paper introduces the research results of various double-patterning techniques toward 22nm nodes and touches upon newly developed elemental technologies for double patterning.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Hidetami Yaegashi, Eiichi Nisimura, Kazuhide Hasebe, Tetsu Kawasaki, Masato Kushibiki, Arisa Hara, Shoichi Yamauchi, Sakurako Natori, Nakajima Shigeru, Hiroki Murakami, Kazuo Yabe, Satoru Shimura, Fumiko Iwao, and Kenichi Oyama "Implementation of double patterning process toward 22-nm node", Proc. SPIE 7520, Lithography Asia 2009, 75201E (11 December 2009); https://doi.org/10.1117/12.839826
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Cited by 2 scholarly publications.
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KEYWORDS
Double patterning technology

Photoresist processing

Silica

Etching

Photoresist materials

Resolution enhancement technologies

Line width roughness

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