Transistor layout configuration effect on actual gate LER

Guy Ayal; Eitan Shauly; Israel Rotshtein; Ovadya Menadeva; Amit Siany; Ram Peltinov; Yosi Shacham-Diamand

doi:10.1117/12.813953

12 March 2009 Transistor layout configuration effect on actual gate LER

Guy Ayal, Eitan Shauly, Israel Rotshtein, Ovadya Menadeva, Amit Siany, Ram Peltinov, Yosi Shacham-Diamand

Proceedings Volume 7275, Design for Manufacturability through Design-Process Integration III; 72750Y (2009) https://doi.org/10.1117/12.813953
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

The importance of Line Edge Roughness (LER) and Line Width Roughness (LWR) has long surpassed its effect on process control. As devices scale down, the roughness effects have become a major hindrance for further advancement along Moore's law. Many studies have been conducted over the years on the sensitivity of LER to various changes in the materials and the process, which have been considered the main way to tackle the problem - especially through Photoresist improvement. However, despite the increased development of DFM tools in recent years, limited research was done as to LER sensitivity to layout, and the research that was done was limited to proximity effects. In this paper, we study the sensitivity of LER to the layout around the transistor, defined by the gate structure of poly over AA (Active Area). Using different types and geometries of transistors, we found that the poly-gate LER is sensitive to the structure of the Active Area around it (source/drain from gate to contact, both shape and length). Using local LER measurement (moving standard deviation of poly edge location), we found a clear correlation between LER value and the length of the AA/STI boundary located at a close range. Longer AA edges yield higher LER, as proved by comparing gate LER of dog-bone transistor with classical transistor. Based on these results, we suggest that LER is sensitive not only to proximity effects, but also to the layout of underlying layers, through the effect of light scattering of the edges during the lithographic process.

Citation Download Citation

Guy Ayal, Eitan Shauly, Israel Rotshtein, Ovadya Menadeva, Amit Siany, Ram Peltinov, and Yosi Shacham-Diamand "Transistor layout configuration effect on actual gate LER", Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72750Y (12 March 2009); https://doi.org/10.1117/12.813953

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available