Variations in timing and leakage power of 45nm library cells due to lithography and stress effects

Kayvan Sadra; Mark Terry; Arjun Rajagopal; Robert A. Soper; Donald Kolarik; Tom Aton; Brian Hornung; Rajesh Khamankar; Philippe Hurat; Bala Kasthuri; Yajun Ran; Nishath Verghese

doi:10.1117/12.816485

12 March 2009 Variations in timing and leakage power of 45nm library cells due to lithography and stress effects

Kayvan Sadra, Mark Terry, Arjun Rajagopal, Robert A. Soper, Donald Kolarik, Tom Aton, Brian Hornung, Rajesh Khamankar, Philippe Hurat, Bala Kasthuri, Yajun Ran, Nishath Verghese

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Proceedings Volume 7275, Design for Manufacturability through Design-Process Integration III; 72750K (2009) https://doi.org/10.1117/12.816485
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

We have conducted a study of context-dependent variability for cells in a 45nm library, including both lithography and stress effects, using the Cadence Litho Electrical Analyzer (LEA) software. Here, we present sample data and address a number of questions that arise in such simulations. These questions include identification of stress effects causing context dependence, impact of the number of contexts on the results, and combining lithography-induced variations due to overlay error with context-dependent variations. Results of such simulations can be used to drive a number of corrective and adaptive actions, among them layout modification, cell placement restrictions, or optimal design margin determination.

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Kayvan Sadra, Mark Terry, Arjun Rajagopal, Robert A. Soper, Donald Kolarik, Tom Aton, Brian Hornung, Rajesh Khamankar, Philippe Hurat, Bala Kasthuri, Yajun Ran, and Nishath Verghese "Variations in timing and leakage power of 45nm library cells due to lithography and stress effects", Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72750K (12 March 2009); https://doi.org/10.1117/12.816485

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