SoC variability evaluation and reduction

Artur P. Balasinski; Michael C. Smayling; Valery Axelrad

doi:10.1117/12.758782

28 December 2007 SoC variability evaluation and reduction

Artur P. Balasinski, Michael C. Smayling, Valery Axelrad

Proceedings Volume 6798, Microelectronics: Design, Technology, and Packaging III; 67980I (2007) https://doi.org/10.1117/12.758782
Event: SPIE Microelectronics, MEMS, and Nanotechnology, 2007, Canberra, ACT, Australia

Abstract

Device parameter variation across the product die and wafer compromises functionality, performance, and yield of integrated devices increasingly more as technology shrinks into the sub-100 nm range. Such variability is of special importance for System-on-Chip products, affecting e.g., frequency response of the analog/RF blocks. Variability reduction can be accomplished through tightening the manufacturing process, adding technology rules for manufacturability (Design-for-Manufacturability, DFM), or developing parameterized, correct by construction (CBC) design or layout (upstream approach). While so far the best option for variability reduction was to improve process capability without resticting product design (downstream approach), it may no longer be preferred due to the continuously increasing process cost driven by technology shrinks. In this work, we discuss a procedure to separate the variability for a 1D and 2D layout due to the lithography and other combined process effects. We then use this procedure to define design rules for analog/RF layout to minimize parametric variability at the minimal cost of the footprint. These rules can be subsequently used to create the CBC design and layout (upstream approach) such that the process window is traded for device footprint by the aggressiveness of the resolution enhancement techniques (e.g., optical proximity correction, OPC). Another option for variability reduction, the layout-time addition of design rules or OPC in response to the localized issues in a random layout (hot spots) causes reworks and delays and is not preferred.

Citation Download Citation

Artur P. Balasinski, Michael C. Smayling, and Valery Axelrad "SoC variability evaluation and reduction", Proc. SPIE 6798, Microelectronics: Design, Technology, and Packaging III, 67980I (28 December 2007); https://doi.org/10.1117/12.758782

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members: $17.00

Non-members: $21.00 ADD TO CART

PROCEEDINGS
8 PAGES

DOWNLOAD PAPER SAVE TO MY LIBRARY

GET CITATION

RIGHTS & PERMISSIONS

Get copyright permission Get copyright permission on Copyright Marketplace

KEYWORDS

Computer aided design

Optical proximity correction

Design for manufacturing

Manufacturing

System on a chip

Calibration

Etching

Show All Keywords

Keywords/Phrases

Search In:

Publication Years