Litho aware method for circuit timing/power analysis through process

R. S. Fathy; M. Al-Imam; H. Diab; M. M. Fakhry; J. A. Torres; B. Graupp; J. M. Brunet; M. S. Bahnas

doi:10.1117/12.711723

21 March 2007 Litho aware method for circuit timing/power analysis through process

R. S. Fathy, M. Al-Imam, H. Diab, M. M. Fakhry, J. A. Torres, B. Graupp, J. M. Brunet, M. S. Bahnas

Proceedings Volume 6521, Design for Manufacturability through Design-Process Integration; 65210O (2007) https://doi.org/10.1117/12.711723
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

Device extraction and the quality of device extraction is becoming of increasing concern for integrated circuit design flow. As circuits become more complicated with concomitant reductions in geometry, the design engineer faces the ever burgeoning demand of accurate device extraction. For technology nodes of 65nm and below approximation of extracting the device geometry drawn in the design layout polygons might not be sufficient to describe the actual electrical behavior for these devices, therefore contours from lithographic simulations need to be considered for more accurate results. Process window variations have a considerable effect on the shape of the device wafer contour, having an accurate method to extract device parameters from wafer contours would still need to know which lithographic condition to simulate. Many questions can be raised here like: Are contours that represent the best lithography conditions just enough? Is there a need to consider also process variations? How do we include them in the extraction algorithm? In this paper we first present the method of extracting the devices from layout coupled with lithographic simulations. Afterwards a complete flow for circuit time/power analysis using lithographic contours is described. Comparisons between timing results from the conventional LVS method and Litho aware method are done to show the importance of litho contours considerations.

Citation Download Citation

R. S. Fathy, M. Al-Imam, H. Diab, M. M. Fakhry, J. A. Torres, B. Graupp, J. M. Brunet, and M. S. Bahnas "Litho aware method for circuit timing/power analysis through process", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210O (21 March 2007); https://doi.org/10.1117/12.711723

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available