Paper
5 April 2007 Use of automated EBR metrology inspection to optimize the edge bead process
Alan Carlson, Tuan Le, Ajay Pai, Joseph Hallen, Bridget Rioux
Author Affiliations +
Abstract
Accurate placement of the edge exclusion region is critical to maintaining edge die yield. Variation in film overlay in the edge exclusion region can lead to yield-limiting defects. Edge Bead Removal (EBR) metrology or Edge Exclusion Width (EEW) metrology describes a topside surface measurement of the wafer edge exclusion region relative to the wafer center and the wafer edge. This measurement is typically made at several points along the wafer's edge and often ranges between 0mm and 6 mm in width. In photolithography, EBR metrology data can be used to determine the repeatability of wafer alignment and the accuracy of EBR dispensing nozzles on the coat track. In addition to EBR/EEW metrology, wafer edge inspection provides an indirect method to control the EBR process by detecting jaggedness of the EBR profile, scalloping, splashing, and other EBR line defects. Improper EBR can also create residuals on other edge surfaces that can lead to cross-contamination of wafers and handling equipment. This paper describes a combined EBR/EEW metrology and wafer edge inspection method that can quickly detect EBR-related defects and characterize the quality of the EBR process. This data reveals the relationship between EBR-related defects and the quality of the EBR process, and can be used to make necessary adjustments to the coat track - and as a basis for wafer rework decisions. Proper tuning and monitoring of the EBR/EEW process allows for the eventual elimination of an entire class of EBR-related defects, thus significantly increasing edge die yield.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Alan Carlson, Tuan Le, Ajay Pai, Joseph Hallen, and Bridget Rioux "Use of automated EBR metrology inspection to optimize the edge bead process", Proc. SPIE 6518, Metrology, Inspection, and Process Control for Microlithography XXI, 65182L (5 April 2007); https://doi.org/10.1117/12.712340
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CITATIONS
Cited by 1 scholarly publication and 2 patents.
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KEYWORDS
Semiconducting wafers

Metrology

Inspection

Optical tracking

Thin film coatings

Process control

Wafer-level optics

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