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The aggressive scaling of VLSI feature size and the pervasive use of advanced reticle enhancement technologies
leads to dramatic increases in mask costs, pushing prototype and low volume production designs at the limit
of economic feasibility. Multiple project wafers (MPW), or "shuttle" runs, provide an attractive solution for
such designs, by providing a mechanism to share the cost of mask tooling among up to tens of designs of the
same technology flow. However, delay cost associated with schedule alignment is ignored in previous work. The
saving on mask cost may be easily surpassed by the profit loss due to the schedule alignment. Therefore, Multi-
flow Multi-layer Multi-project Reticles (MFMLMPR) become a more viable mask-cost saving technique for low
volume production since it share the mask cost between different layers of the same design and between designs
of different technology flows. However, MFMLMPR design introduce complexities not encountered in traditional
single-flow or single-layer reticles.
In this paper we propose the first design flow for MFMLMPR aimed at minimizing the total manufacturing
cost (including mask cost, wafer cost and delay cost) to fulfill given die production volumes. Our flow includes
three main steps: (1) schedule-aware project partitioning with multi-flow embedding (2) multi-frame reticle
design, and (3) multi-project frame floorplanning. Our contributions are as follows. For the first step, a fast
iterative matching algorithm is proposed to calculate the mask cost for multi-flow embedding with consideration
of all practical manufacturing costs. We then propose an integer linear programming (ILP) based method for
optimal manufacturing cost minimization. Since ILP suffers from impractically long runtimes when the number
of projects is large, we propose a sliding time window heuristic to exhaustively search the solution space for the
best tradeoff between mask cost and delay cost. For the second step, we propose an ASAP frame embedding
heuristic to minimize the mask cost. Finally, a "generalized chessboard" floorplan with simulated annealing is
proposed to generate more dicing friendly frame floorplans for multi-flow projects, observing given maximum
reticle sizes.
We have tested our flow on production industry testcases. The experimental results show that our schedule-aware
project partitioner yields an average reduction of 58.4% in manufacturing cost. The reduction of mask cost
is around 46.3% compared with use of traditional layer-by layer checking methods. Our generalized chessboard
floorplanner leads to an average reduction of 22.8% in the required number of wafers compared to the previous
best reticle floorplanner.
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