Paper
10 June 2006 Simulation of the vertical MOSFET with electrically variable source-drain junctions
I. A. Horin, A. A. Orlikovsky, A. E. Rogozhin, A. G. Vasiliev
Author Affiliations +
Proceedings Volume 6260, Micro- and Nanoelectronics 2005; 62601R (2006) https://doi.org/10.1117/12.683554
Event: Micro- and Nanoelectronics 2005, 2005, Zvenigorod, Russian Federation
Abstract
Vertical MOSFET with electrically variable source-drain junctions has been simulated in ISE TCAD. Novel structure has been developed thoroughly. New concepts and materials like high-k and silicide have been used. For the present some electrical characteristics have been investigated by modeling. Marginal on-off drain current values has been obtained and analyzed. Parasitic capacitance, resistances and time delays have been calculated. As a result, the vertical MOSFET with electrically variable junctions has excellent electrical characteristics and very high cut-off frequency.
© (2006) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
I. A. Horin, A. A. Orlikovsky, A. E. Rogozhin, and A. G. Vasiliev "Simulation of the vertical MOSFET with electrically variable source-drain junctions", Proc. SPIE 6260, Micro- and Nanoelectronics 2005, 62601R (10 June 2006); https://doi.org/10.1117/12.683554
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KEYWORDS
Field effect transistors

Transistors

Diffusion

Capacitance

Resistance

Silicon

Doping

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