Defect metrology challenges at 45-nm technology node and beyond

Dilip Patel; Jeffrey Hanrahan; Kyuhong Lim; Milton Godwin; Peter Figliozzi; Dale Sheu

doi:10.1117/12.664190

24 March 2006 Defect metrology challenges for the 45-nm technology node and beyond

Dilip Patel, Jeffrey Hanrahan, Kyuhong Lim, Milton Godwin, Peter Figliozzi, Dale Sheu

Proceedings Volume 6152, Metrology, Inspection, and Process Control for Microlithography XX; 615207 (2006) https://doi.org/10.1117/12.664190
Event: SPIE 31st International Symposium on Advanced Lithography, 2006, San Jose, California, United States

Abstract

Without the ability to detect potential yield-limiting defects in-line, the yield learning cycle is severely crippled, compromising the financial success of chip makers. As design rules shrink, device yield is seriously affected by smaller size particle and patterned defects that were not important in the past. These mechanisms are becoming more difficult to detect with current defect detection tools and techniques. The optical defect inspection tools that are currently available do not adequately detect defects, while scanning electron microscope (SEM) based inspection tools are too slow. With each successive technology node, optical inspection becomes less capable relative to the previous technology. As sensitivity is increased to detect smaller defects, the nuisance defect rate increases commensurately. Line-edge roughness (LER) and subtle process variations are making it more difficult to detect defects of interest (DOI). Smaller defects mean smaller samples available for energy dispersive x-ray analysis (EDX), necessitating an improved or new methodology for elemental analysis. This paper reviews these and some other challenges facing defect metrology at the 45nm technology node and beyond. The challenges in areas of patterned and unpatterned wafer inspection, defect review, and defect characterization are outlined along with proposed solutions. It also provides an overview of several ongoing projects conducted at International SEMATECH Manufacturing Initiative (ISMI) to address these challenges.

Citation Download Citation

Dilip Patel, Jeffrey Hanrahan, Kyuhong Lim, Milton Godwin, Peter Figliozzi, and Dale Sheu "Defect metrology challenges for the 45-nm technology node and beyond", Proc. SPIE 6152, Metrology, Inspection, and Process Control for Microlithography XX, 615207 (24 March 2006); https://doi.org/10.1117/12.664190

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members: $17.00

Non-members: $21.00 ADD TO CART

PROCEEDINGS
10 PAGES

DOWNLOAD PAPER SAVE TO MY LIBRARY

GET CITATION

RIGHTS & PERMISSIONS

Get copyright permission Get copyright permission on Copyright Marketplace

KEYWORDS

Defect detection

Semiconducting wafers

Inspection

Scanning electron microscopy

Target recognition

Metrology

Manufacturing

Show All Keywords

Keywords/Phrases

Search In:

Publication Years