Hardware implementation of the wavelet transform for JPEG2000

J. Hormigo; J. M. Prades; J. Villalba; E. Zapata

doi:10.1117/12.608221

30 June 2005 Hardware implementation of the wavelet transform for JPEG2000

J. Hormigo, J. M. Prades, J. Villalba, E. Zapata

Proceedings Volume 5837, VLSI Circuits and Systems II; (2005) https://doi.org/10.1117/12.608221
Event: Microtechnologies for the New Millennium 2005, 2005, Sevilla, Spain

Abstract

In this paper we shall propose and examine an VLSI architecture for the integer-to-integer wavelet transform which is used by JPEG2000 standard for lossless compression. In order to achieve a fully utilization of hardware resources independently of the bit-depth of the input data, on-line arithmetic (digit-serial computation) is proposed to carry out this architecture. Besides, a high throughput is achieved thanks to the high degree of parallelism that on-line arithmetic allows. The design has been simulated and implemented using Xilinx FPGA device, and its main results are provided.

Citation Download Citation

J. Hormigo, J. M. Prades, J. Villalba, and E. Zapata "Hardware implementation of the wavelet transform for JPEG2000", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); https://doi.org/10.1117/12.608221

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