Design and modeling of an on-silicon spiral inductor library using improved EM simulations

A. Goni-Iturri; S. L. Khemchandani; F. J. del Pino; J. Garcia; B. Gonzalez; A. Hernandez

doi:10.1117/12.608292

30 June 2005 Design and modeling of an on-silicon spiral inductor library using improved EM simulations

A. Goni-Iturri, S. L. Khemchandani, F. J. del Pino, J. Garcia, B. Gonzalez, A. Hernandez

Proceedings Volume 5837, VLSI Circuits and Systems II; (2005) https://doi.org/10.1117/12.608292
Event: Microtechnologies for the New Millennium 2005, 2005, Sevilla, Spain

Abstract

This paper deals with the design and modeling of integrated spiral inductors for RF applications by means of a general purpose Electromagnetic (EM) simulator. These tools allow optimizing flexibly the inductor layout structure. The inductor performance can be obtained by using a three-dimensional design tool or a two-dimensional one. Planar 2-D or so called 2.5-Ds simulators are faster and accept complex coil geometries. We have used one of these simulators, the Advanced Design System planar EM simulator, Momentum, from Agilent. The inductor quality factor (Q) is limited, among other phenomena, by the series resistance of the metal traces and the substrate losses. Therefore the simulator requires an accurate set up of the process and simulator parameters and a correct algorithm to model metal thickness to rely on simulation results. In this paper we analyze and compare these different approaches. A high-quality factor inductor library on a 0.35 μm SiGe technology at 5 GHz is also designed in this work using the proper simulator set up. Nine of the inductors have been fabricated and measured to test the simulator reliability. Measurements taken over a frequency range from 500 MHz to 10GHz show a good agreement with 2.5-EM simulations.

Citation Download Citation

A. Goni-Iturri, S. L. Khemchandani, F. J. del Pino, J. Garcia, B. Gonzalez, and A. Hernandez "Design and modeling of an on-silicon spiral inductor library using improved EM simulations", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); https://doi.org/10.1117/12.608292

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