A complete hardening method for the generation of fault tolerant circuits

Marta Portela-Garcia; Mario Garcia-Valderas; Celia Lopez-Ongil; Luis Entrena

doi:10.1117/12.608332

30 June 2005 A complete hardening method for the generation of fault tolerant circuits

Marta Portela-Garcia, Mario Garcia-Valderas, Celia Lopez-Ongil, Luis Entrena

Proceedings Volume 5837, VLSI Circuits and Systems II; (2005) https://doi.org/10.1117/12.608332
Event: Microtechnologies for the New Millennium 2005, 2005, Sevilla, Spain

Abstract

Fault Tolerance has become an important requirement for integrated circuits, not only in safety critical applications like aerospace circuits, but also for applications working at the earth surface. Since the appearance of nanometer technologies, the sensitiveness of integrated circuits to radiation has increased notably, making the occurrence of soft errors much more frequent. Therefore, hardened circuits are currently required in many applications where fault tolerance was not a requirement in the very near past. In this paper, tools and methods for the whole hardening process of a circuit are presented: tools for the automatic insertion of fault tolerant structures in a circuit description and methods for the evaluation of fault tolerance achieved. These methods allow the evaluation of fault tolerance by means of emulation in platform FPGAs, which offer a much faster way to perform evaluation than simulation based techniques. Different circuits are used to test the proposed tool for inserting fault tolerant structures. Fault tolerance evaluation is performed using the proposed fault emulation methods, before and after applying hardening process, showing the fault tolerance improvement. The proposed techniques for evaluation have been compared, in terms of evaluation time, with previously proposed solutions and with simulation based solutions, showing improvements of several orders of magnitude.

Citation Download Citation

Marta Portela-Garcia, Mario Garcia-Valderas, Celia Lopez-Ongil, and Luis Entrena "A complete hardening method for the generation of fault tolerant circuits", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); https://doi.org/10.1117/12.608332

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