Hardware acceleration and verification of systems designed with hardware description languages (HDL)

Remigiusz Wisniewski; Marek Wegrzyn

doi:10.1117/12.610689

23 February 2005 Hardware acceleration and verification of systems designed with hardware description languages (HDL)

Remigiusz Wisniewski, Marek Wegrzyn

Proceedings Volume 5775, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments III; (2005) https://doi.org/10.1117/12.610689
Event: Wilga 2004, 2004, Wilga, Poland

Abstract

Hardware description languages (HDLs) allow creating bigger and bigger designs nowadays. The size of prototyped systems very often exceeds million gates. Therefore verification process of the designs takes several hours or even days. The solution for this problem can be solved by hardware acceleration of simulation.

Citation Download Citation

Remigiusz Wisniewski and Marek Wegrzyn "Hardware acceleration and verification of systems designed with hardware description languages (HDL)", Proc. SPIE 5775, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments III, (23 February 2005); https://doi.org/10.1117/12.610689

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