Advanced process control for deep sub-100nm gate fabrication

Takeshi K. Goto; Mitsugu Tajima; Fukashi Harada; Takaya Kato; Takahiro Yamazaki; Takao Taguchi

doi:10.1117/12.599284

17 May 2005 Advanced process control for deep sub-100nm gate fabrication

Takeshi K. Goto, Mitsugu Tajima, Fukashi Harada, Takaya Kato, Takahiro Yamazaki, Takao Taguchi

Proceedings Volume 5755, Data Analysis and Modeling for Process Control II; (2005) https://doi.org/10.1117/12.599284
Event: Microlithography 2005, 2005, San Jose, California, United States

Abstract

We developed advanced process control (APC); run-by-run model based process control (RbR MBPC) system for deep sub-100nm gate fabrication of CMOS logic ships, designed in order to achieve lot-to-lot variance of gate line width within ±1nm, using critical dimension measurement scanning electron microscope (CD-SEM). Using a lot-mean resist linewidth (pre-etch CD), gate etching plasma condition can be modified to control poly-silicon gate linewidth (post-etch CD) on target. Using etching shift amount of a pilot-wafer within a processing lot, model in the MBPC can be updated to avoid changes of the intercept of the model that is linear equation. The MBPC system was applied to deep sub-100nm gate fabrication and was tested using test lots of 73 to evaluate performance. At an initial lot-mean pre-etch CDs spread of 9.31 nm, the lot-mean post-etch CDs spread was reduced to range of 2.49 nm and its variance was 0.55 nm of 1σ. The range of the linear equation intercept was 8.12 nm and then the range of the prediction errors of feedback control was 2.26 nm, which is originated from both the 1st wafer effect of a pilot wafer of processing lot and measurement CD errors. We found that the prediction error is the largest in errors of the MBPC system. The prediction of model intercept is crucial in the MBPC system in order to achieve lot-to-lot variance of gate line width within ±1nm for gate etching fabrication.

Citation Download Citation

Takeshi K. Goto, Mitsugu Tajima, Fukashi Harada, Takaya Kato, Takahiro Yamazaki, and Takao Taguchi "Advanced process control for deep sub-100nm gate fabrication", Proc. SPIE 5755, Data Analysis and Modeling for Process Control II, (17 May 2005); https://doi.org/10.1117/12.599284

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KEYWORDS

Etching

Semiconducting wafers

Critical dimension metrology

Cadmium

Error analysis

Plasma etching

Process control

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