Novel loop output buffer architecture and scheduling for efficient contention resolution in optical packet switching

Pengcheng Xiao; Qingji Zeng; Jun Huang; Jimin Liu

doi:10.1117/12.510880

19 August 2003 Novel loop output buffer architecture and scheduling for efficient contention resolution in optical packet switching

Pengcheng Xiao, Qingji Zeng, Jun Huang, Jimin Liu

Author Affiliations +

Proceedings Volume 5247, Optical Transmission Systems and Equipment for WDM Networking II; (2003) https://doi.org/10.1117/12.510880
Event: ITCom 2003, 2003, Orlando, Florida, United States

Abstract

A new loop output buffer architecture for optical packet switching is proposed. It is consisted of multiplex FDL loops, which are divided into k stages by k (M+1) x (M+1) switches. Using this architecture, a few FDL loops can provide large optical memories and get good packet-loss performance, and the delay performance can be improved by adding switches and buffer scheduling.

Citation Download Citation

Pengcheng Xiao, Qingji Zeng, Jun Huang, and Jimin Liu "Novel loop output buffer architecture and scheduling for efficient contention resolution in optical packet switching", Proc. SPIE 5247, Optical Transmission Systems and Equipment for WDM Networking II, (19 August 2003); https://doi.org/10.1117/12.510880

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