Macromodel for exact computation of propagation delay time in GaAs and CMOS technologies

Jose C. Garcia; Juan A. Montiel-Nelson; Javier Sosa; Hector Navarro; Roberto Sarmiento

doi:10.1117/12.498586

21 April 2003 Macromodel for exact computation of propagation delay time in GaAs and CMOS technologies

Jose C. Garcia, Juan A. Montiel-Nelson, Javier Sosa, Hector Navarro, Roberto Sarmiento

Proceedings Volume 5117, VLSI Circuits and Systems; (2003) https://doi.org/10.1117/12.498586
Event: Microtechnologies for the New Millennium 2003, 2003, Maspalomas, Gran Canaria, Canary Islands, Spain

Abstract

A new transient macromodel for the cells used in DCFL GaAs and CMOS digital design is introduced in this paper. The numerical solution determines accurate propagation delay times. The macromodel is based on the differential equation for the output voltage in terms of currents and capacitances. An straightforward treatment of the differential equation for an inverter in DCFL GaAs and CMOS has been obtained. It could be resolved numerically by a 4th order Runge Kutta method. Good agreement is obtained between the HSPICE simulation and the computation of the propagation delays for DCFL GaAs and CMOS basic gates: INV, NOR, OR and NAND. There is no error between HSPICE and our computation of propagation delay time for the high to low (tphl) and low to high (tplh) transitions. The propagation delay times for two types of transition were measured and compared with HSPICE. The results demonstrate that our approach matches with HSPICE with no error. The numerical method was programmed in C language. In addition, computation time analysis is provided and numerical solution is several orders of magnitude faster than HSPICE. Work is in progress to obtain the macromodel of a standard cell library for digital application both for a 0.6 microns E/D GaAs process (H-GaAsIV) from Vitesse Semiconductor and for a 0.18 microns logic/mixed-signal CMOS process (1P6M) from TSMC Corp.

Citation Download Citation

Jose C. Garcia, Juan A. Montiel-Nelson, Javier Sosa, Hector Navarro, and Roberto Sarmiento "Macromodel for exact computation of propagation delay time in GaAs and CMOS technologies", Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); https://doi.org/10.1117/12.498586

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KEYWORDS

Gallium arsenide

Differential equations

Transistors

Numerical analysis

Logic

Capacitance

Field effect transistors

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