Silicon-on-insulator (SOI) wafer fabrication for MEMS applications

Bhimanadhuni R. KotiReddy; Parimi Ramaseshagiri Rao; Amitava DasGupta; Kunchinadka Narayana Hari Bhat

doi:10.1117/12.514719

14 October 2003 Silicon-on-insulator (SOI) wafer fabrication for MEMS applications

Bhimanadhuni R. KotiReddy, Parimi Ramaseshagiri Rao, Amitava DasGupta, Kunchinadka Narayana Hari Bhat

Proceedings Volume 5062, Smart Materials, Structures, and Systems; (2003) https://doi.org/10.1117/12.514719
Event: Smart Materials, Structures, and Systems, 2002, Bangalore, India

Abstract

In this paper, it is shown that Silicon-On-Insulator (SOI) wafers with good surface finish and thickness control can be realized using Silicon Fusion Bonding along with an optimized ethylenediamine-pyrocatechol-water (EDP) etching approach. Single crystal diaphragms of 11 μm thickness have been fabricated using these SOI wafers. These diaphragms were tested and found to withstand N₂ gas pressures in excess of 260 psi without rupturing.

Citation Download Citation

Bhimanadhuni R. KotiReddy, Parimi Ramaseshagiri Rao, Amitava DasGupta, and Kunchinadka Narayana Hari Bhat "Silicon-on-insulator (SOI) wafer fabrication for MEMS applications", Proc. SPIE 5062, Smart Materials, Structures, and Systems, (14 October 2003); https://doi.org/10.1117/12.514719

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