Optimized thick film processing for bumping layers

Stanley F. Wanat; Robert Plass; Ernesto S. Sison; Hong Zhuang; Ping-Hung Lu; Clifford Hamel; Jeffrey M. Guevremont

doi:10.1117/12.485181

12 June 2003 Optimized thick film processing for bumping layers

Stanley F. Wanat, Robert Plass, Ernesto S. Sison, Hong Zhuang, Ping-Hung Lu, Clifford Hamel, Jeffrey M. Guevremont

Proceedings Volume 5039, Advances in Resist Technology and Processing XX; (2003) https://doi.org/10.1117/12.485181
Event: Microlithography 2003, 2003, Santa Clara, California, United States

Abstract

As information densities increase with each generation of microchips, there is a concurrent reduction in feature sizes and even chip dimensions. With reduced chip sizes, the horizontal space for connectors on the back side of the chips is also limited. Most resists are not thick enough to accommodate the height of the connector posts needed. As a consequence, the plated posts or “bumps” overfill the imaged via holes thereby providing a mushroom effect that reduces usable horizontal space for other connectors. We have formulated a high solids photoresist (AZ 50 XT) capable of depositing 60-90μm single coat resist films. By optimizing processing conditions, reasonably straight side-wall geometries are possible. The importance of processing parameters (baking, exposure and development) are heightened by the inherent difficulty in balancing residual solvent against reasonable processing times needed for commercial use. This paper summarizes a joint program between Clariant and SUSS Microtec in optimizing the use of AZ 50 XT resist for bumping layer applications.

Citation Download Citation

Stanley F. Wanat, Robert Plass, Ernesto S. Sison, Hong Zhuang, Ping-Hung Lu, Clifford Hamel, and Jeffrey M. Guevremont "Optimized thick film processing for bumping layers", Proc. SPIE 5039, Advances in Resist Technology and Processing XX, (12 June 2003); https://doi.org/10.1117/12.485181

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