Paper
2 June 2003 Performance study of new segmented overlay marks for advanced wafer processing
Mike Adel, John A. Allgair, David C. Benoit, Mark Ghinovker, Elyakim Kassel, C. Nelson, John Charles Robinson, Gary Stanley Seligman
Author Affiliations +
Abstract
We explore the implementation of improved overlay mark designs increasing mark fidelity and device correlation for advanced wafer processing. The effect of design rule segmentation on overlay mark performance is studied. Short loop wafers with 193 nm lithography for front-end (poly to STI active) as well as back-end (via to metal) were processed and evaluated. A comparison of 6 different box-in-box (BiB) overlay marks, including non-segmented, multi bar, and design-rule segmented were compared to several types of AIM (Advanced Imaging Metrology) grating targets which were non-segmented and design rule segmented in various ways. The key outcomes of the performance study include the following: the total measurement uncertainty (TMU) was estimated by the RMS of the precision, TIS 3-sigma and overlay mark fidelity (OMF). The TMU calculated in this way show a 40% reduction for the grating marks compared to BiB. The major contributors to this performance improvement were OMF and precision, which were both improved by nearly a factor of 2 on the front-end layer. TIS-3-sigma was observed to improve when design rule segmentation was implemented, while OMF was marginally degraded. Similar results were found for the back end wafers. Several different pitches and segmentation schemes were reviewed and this has allowed the development of a methodology for target design optimization. Resulting improvements in modeled residuals were also achieved.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Mike Adel, John A. Allgair, David C. Benoit, Mark Ghinovker, Elyakim Kassel, C. Nelson, John Charles Robinson, and Gary Stanley Seligman "Performance study of new segmented overlay marks for advanced wafer processing", Proc. SPIE 5038, Metrology, Inspection, and Process Control for Microlithography XVII, (2 June 2003); https://doi.org/10.1117/12.483477
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Cited by 15 scholarly publications.
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KEYWORDS
Overlay metrology

Semiconducting wafers

Metrology

Optical design

Data modeling

Lithography

Metals

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