Constant-delay MSB-first bit-serial adder

Chang Yong Kang; Earl E. Swartzlander Jr.

doi:10.1117/12.451778

6 December 2002 Constant-delay MSB-first bit-serial adder

Chang Yong Kang, Earl E. Swartzlander Jr.

Proceedings Volume 4791, Advanced Signal Processing Algorithms, Architectures, and Implementations XII; (2002) https://doi.org/10.1117/12.451778
Event: International Symposium on Optical Science and Technology, 2002, Seattle, WA, United States

Abstract

A new MSB-first bit-serial adder/subtracter architecture is proposed. The architecture utilizes a modified Manchester carry chain to accommodate the carry from the future LSB's. The carry chain is shown to have the constant delay of two AND gates and one XOR gate regardless of the operand width, which allows a fast constant operational clock frequency. When compared to the conventional parallel addition approach where the operand bits are stored and then added in parallel, the proposed architecture also provides a significant area saving. It is also shown that the proposed architecture can be generalized for radix-r operands.

Citation Download Citation

Chang Yong Kang and Earl E. Swartzlander Jr. "Constant-delay MSB-first bit-serial adder", Proc. SPIE 4791, Advanced Signal Processing Algorithms, Architectures, and Implementations XII, (6 December 2002); https://doi.org/10.1117/12.451778

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available