Robust methodology for state-of-the-art embedded SRAM bitcell design

Mark J. Craig; John S. Petersen; Joshua Lund; David J. Gerold; Nien-Po Chen

doi:10.1117/12.475696

12 July 2002 Robust methodology for state-of-the-art embedded SRAM bitcell design

Mark J. Craig, John S. Petersen, Joshua Lund, David J. Gerold, Nien-Po Chen

Proceedings Volume 4692, Design, Process Integration, and Characterization for Microelectronics; (2002) https://doi.org/10.1117/12.475696
Event: Design, Process Integration, and Characterization for Microelectronics, 2002, Santa Clara, CA, United States

Abstract

A design and verification methodology of advanced SRAM bitcell design is described. Dense bitcells, drawn for embedded SRAM memory applications, are drawn and simulated for cell functionality and stability. After first-pass design, lithography correction is determined using analytical and iterative simulation routines. Analytical corrections are tailored to comprehend not only specific tool and material platforms associated with the process technology, but are also optimized to account for process integration issues arising from mask layer to mask layer interactions. Lithography process windows are modeled though simulations based on specific stepper illumination scheme, and material systems. Process integration windows are modeled through overlay of simulated patterns while taking into account process control limits of misalignment and critical dimension. Comparison of simulated to electrical bitcell results are discussed and manufacturability considerations are addressed through electrical responses of bitcell-specific diagnostic test structures.

Citation Download Citation

Mark J. Craig, John S. Petersen, Joshua Lund, David J. Gerold, and Nien-Po Chen "Robust methodology for state-of-the-art embedded SRAM bitcell design", Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); https://doi.org/10.1117/12.475696

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