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In this paper, we discuss rule-based and model-based tiling methodologies for interconnect layers and their implications for design flows and performance. The addition of these 'dummy' tiling metal features modifies the final physical design and reduces the variation of back-end process parameters. This is a newly developing area of design flow and its importance is increasing with each succeeding semiconductor generation. Along with this development new methodologies and tools need to be introduced to handle time placement post-physical design, as well as efficient methods for representing the resulting large amount of dat. Additionally, the inclusion of tiles may introduce performance-degrading parasitic effects. The situation is complicated by the order of the elements of the design flow: parasitics characterization requires knowledge about the placement of dummy metal times, which takes place after physical design. In this study, we co pare the advantages of having uniform interconnect characteristics to the performance degradation caused by the additional layout parasitics. We also discuss several possible scenarios for the modification of design flows to account for these effects the thereby recover timing and power targets closure. These scenarios depend for their success on the very different length scales of polish and electromagnetic effects. Finally, an analysis of correlations in the parameters that define design corners leads to the new conclusion that the negative effect of increased parasitic loading due to tiling is not as sever as a simple analysis would suggest. This result is due to the fact that the tiling parasitic loading is somewhat compensated for by the improved planarity resulting from tiling, which tightens the process variation-induced spread of metal electrical parameters.
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