Gate line edge roughness effects in 50-nm bulk MOSFET devices

Shiying Xiong; Jeffrey Bokor; Qi Xiang; Philip Fisher; Ian M. Dudley; Paula Rao

doi:10.1117/12.473517

16 July 2002 Gate line-edge roughness effects in 50-nm bulk MOSFET devices

Shiying Xiong, Jeffrey Bokor, Qi Xiang, Philip Fisher, Ian M. Dudley, Paula Rao

Proceedings Volume 4689, Metrology, Inspection, and Process Control for Microlithography XVI; (2002) https://doi.org/10.1117/12.473517
Event: SPIE's 27th Annual International Symposium on Microlithography, 2002, Santa Clara, California, United States

Abstract

We studied gate line edge roughness (LER) and its effect on electrical characteristics of 50nm bulk MOSFETs. Using simulation, we studied the underlying mechanism of three significant LER effects on the electrical performance of advanced 50 nm gate length bulk devices. First, we found that off-state leakage current is much more sensitive than the on-state drive current to gate LER. Second, we found that high frequency LER can lead to a decrease in effective channel length by enhanced lateral diffusion of the self-aligned source/drain extension. Third, low frequency LER causes local CD variation simply due to the statistical variation of average CD in a finite width sample. We also show how device design parameters, such as halo implant dose, can be used to tradeoff LER sensitivity and device performance.

Citation Download Citation

Shiying Xiong, Jeffrey Bokor, Qi Xiang, Philip Fisher, Ian M. Dudley, and Paula Rao "Gate line-edge roughness effects in 50-nm bulk MOSFET devices", Proc. SPIE 4689, Metrology, Inspection, and Process Control for Microlithography XVI, (16 July 2002); https://doi.org/10.1117/12.473517

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