Fast multiply-accumulate architecture

Robert T. Grisamore; Earl E. Swartzlander Jr.

doi:10.1117/12.406506

13 November 2000 Fast multiply-accumulate architecture

Robert T. Grisamore, Earl E. Swartzlander Jr.

Proceedings Volume 4116, Advanced Signal Processing Algorithms, Architectures, and Implementations X; (2000) https://doi.org/10.1117/12.406506
Event: International Symposium on Optical Science and Technology, 2000, San Diego, CA, United States

Abstract

A high speed multiplier-accumulator (MAC) architecture is presented that accepts up to 2^k pairs of n-bit 2's complement input operands and generates one 2n+k-bit result. The implementation uses a 2 stage pipelined multiplier with Dadda reduction and a single carry propagating adder. A significant speedup is achieved with this implementation over conventional MAC designs. The complexity is reduced slightly. An example design is presented with 24-bit input operands designed using a 0.35 micrometer CMOS technology.

Citation Download Citation

Robert T. Grisamore and Earl E. Swartzlander Jr. "Fast multiply-accumulate architecture", Proc. SPIE 4116, Advanced Signal Processing Algorithms, Architectures, and Implementations X, (13 November 2000); https://doi.org/10.1117/12.406506

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